Digital systems design
EE-334
General Information
Welcome to the Digital System Design Course
This course is about the design and implementation of digital microelectronic systems using programmable logic devices (FPGAs). It explains the foundations of synchronous digital circuits and how to implement them using VHDL as a hardware description language that is also the basis for the design of VLSI circuits. You will also learn about the tools and methodology required for implementation on FPGAs. The class includes labs with a state-of-the-art FPGA for guided exercises and a final project.
- Course Organization The course will be held only i... (Text and media area)
- Organizational Material (Text and media area)
- Announcements / Organization (Forum)
- Course Forum (Q&A) (Forum)
- Course plan and schedule 2024 (File)
- Group Inscription for Labs and Exercises: DSD (Group choice)
- Using EMACS to Edit VHDL Code (URL)
- Computers Practical works can be done from one of ... (Text and media area)
- Working with your own computer (Page)
- Working on linux servers (please ask for an edauser account in class beforehand) (Page)
- WinSCP for filesharing (for users of Linux servers with a personal Windows computer) (Page)
- VHDL Resources Here are the main recommended re... (Text and media area)
- Downloadable Material (Text and media area)
- dsd_template (File)
- Information for MNIS Students (Text and media area)
- Welcome & Information for MNIS Students (File)
- Legal Statements on EDA (Text and media area)
- Signature Required : statement on the utilization of EDA and Design Kits in EPFL (File)
- EDA in EPFL : legal considerations (File)
- edauser account reference sheet Winter 2024 (for TA's eyes) (File)
- Wednesday, 11.09. : Lecture / Exercise Session Tim... (Text and media area)
- Slides: Organization and Syllabusof the Course (File)
- Slides: Design of Digital Systems on Component Level (File)
- Recording 2020: Design of Digital Systems on Component Level (URL)
- Slides: Synchronous Digital Circuits and RTL Design (File)
- Recording 2020: Synchronous Digital Circuits and RTL Design (URL)
- Exercise 1 (Text and media area)
- Exercise 1a: Architecture of Digital Systems (File)
- Datasheets (Folder)
- Exercise 1b: Basic Synchronous Digital Circuits and RTL Design (File)
- Exercise 1a: Solution (File)
- Recording (2020): Solution for Exercise 1a: Architecture of Digital Systems (URL)
- Exercise 1b: Solution (File)
- Recording 2020: Solution for Exercise 1b: Basic Synchronous Digital Circuits and RTL Design (URL)
- Wednesday, 18.09.: Lecture / Lab Session Time/Loca... (Text and media area)
- Slides: Introduction to FPGAs (File)
- Recording (2020): Introduction to FPGAs (URL)
- Slides: Hardware Description Languages and HDL Design Flow (File)
- Recording (2020): Hardware Description Languages and HDL Design Flow (URL)
- Slides: Introduction to VHDL - Basic Language Elements (Entity, Architecture, Signals) (File)
- Recording (2020): Introduction to VHDL - Basic Language Elements (Entity, Architecture, Signals) (URL)
- Recording (2020): VHDL Packages (URL)
- Lab 1 (Text and media area)
- Recording (2020): Information on the Organization of the Lab (URL)
- DSD-Lab1 Vivado Tutorial (File)
- lab01 vivado tutorial (File)
- Wednesday, 25.09.: Lecture / Exercise Session Time... (Text and media area)
- Slides: VHDL for Synthesis (2024) (File)
- Recording: VHDL for Synthesis (2020) (URL)
- Slides: More VHDL for Synthesis (Processes & Sequential Statements) (File)
- Recording: More VHDL for Synthesis (Processes & Sequential Statements) (2020) (URL)
- Exercise 2 (Text and media area)
- Exercise 2: RTL Diagram for PWM LED Color Controller (preparation for next Lab) (File)
- Exercise 2 Solution: Led PWM (Theory) (File)
- Recording: Exercise 2 Solution - RTL Diagram for PWM LED Color Controller (preparation for next Lab) (URL)
- Wednesday, 02.10.: Exercise / Lab Session Time/Loc... (Text and media area)
- Exercise 3 (Text and media area)
- Exercise 3: VHDL to Schematics (File)
- Exercise 3: Code - ZIP (File)
- Solution: Exercise 3 (File)
- Solution: Exercise 3 (VHDL Code) (File)
- Solution Slides: Exercise 3 (shown 03/11/21) (File)
- Lab 2 (Text and media area)
- DSD-Lab2 PWM for LED Control - PDF (File)
- DSD-Lab2 PWM for LED Control - ZIP (File)
- Solution: Lab 2 (File)
- Solution: Lab 2 (VHDL Code) (File)
- Recording: Lab 2 Solution - PWM for LED Control - VHDL Coding (URL)
- Wednesday, 09.10.: Lecture / Exercise Session Time... (Text and media area)
- Slides: Finite State Machines Theory and VHDL Coding (File)
- Slides: VHDL for Simulation and Testbenches (File)
- Recording: Finite State Machines Theory and VHDL Coding (URL)
- Recording: VHDL for Simulation and Testbenches (URL)
- Exercise 4 (Text and media area)
- Exercise 4: Finite State Machine (Door Lock) (File)
- Exercise 4 Solution: Finite State Machine (Door Lock) (File)
- Recording (2020): Exercise 4 Solution - Finite State Machine (Door Lock) (URL)
- Wednesday, 16.11.: Lecture / Exercise Session Time... (Text and media area)
- Slides: Static Timing Analysis (File)
- Recording: Static Timing Analysis (URL)
- Slides: From Algorithms to Architectures - Part 1 (File)
- Recording: From Algorithms to Architectures - Part 1 (URL)
- Exercise 5 (Text and media area)
- Exercise 5: Timing Analysis of Synchronous Circuits (File)
- Exercise 5 Solution: Timing Analysis of Synchronous Circuits (File)
Holidays
- Wednesday, 16.10.: Lab Session Time/Location: Lab ... (Text and media area)
- Lab Session 3 (Text and media area)
- DSD-Lab3 KeyLock (FPGA Implementation) - PDF (File)
- DSD-Lab3 KeyLock (FPGA Implementation) - ZIP (File)
- Solution: Lab 3 Keylock in VHDL and on FPGA (shown 03/11/21) (File)
- Solution: Lab 3 (VHDL Code) (File)
- Recording: Lab 3 Solution - Keylock in VHDL and on FPGA (URL)
- Wednesday, 05.11.: Lecture / Exercise Session Time... (Text and media area)
- Slides: From Algorithms to Architectures - Part 2 (File)
- Recording: From Algorithms to Architectures - Part 2a (URL)
- Recording: From Algorithms to Architectures - Part 2b (URL)
- Slides: From Algorithms to Architectures 3 (no Video) (File)
- Exercise 6 (Text and media area)
- Exercise 6: From Algorithms to Architectures (Datapath) (File)
- Exercise 6 Solution: From Algorithms to Architectures (Datapath) (File)
- Wednesday, 12.11.: Lecture & Lab Session Time/Loca... (Text and media area)
- Lab Session 4 (Text and media area)
- DSD-Lab4 Arbiter - PDF (File)
- DSD-Lab4 Arbiter - ZIP (File)
- Solution: Lab 4 Arbiter (File)
- Solution: Lab 4 (VHDL code) (File)
- Recording Lab 4 Solution: Arbiter (URL)
- Wednesday, 22.11.: Lecture / Lab Session (Project)... (Text and media area)
- Slides: Video Interface & VGA (File)
- FINAL PROJECT (GRADED) (Text and media area)
- Slides: Final Project Information (File)
- Handout: Graded Project Information (File)
- Lab Session 5 (Text and media area)
- DSD-Lab5 VGA - PDF (File)
- DSD-Lab5 VGA - ZIP (File)
- Recording: Generating a Clock Generator IP in Vivado (URL)
- Lab Session 6 (Text and media area)
- DSD-Lab6 Memory - PDF (File)
- DSD-Lab6 Memory - ZIP (File)
- Recording: Generating a Memory IP in Vivado (URL)
- Wednesday, 29.11.: Lab Session (Project) Time/Loca... (Text and media area)
- Lab Session 7 (Text and media area)
- DSD-Lab7 Pong Game - PDF (File)
- DSD-Lab7 Pong Game - ZIP (File)
- Wednesday, 4.12.: Lecture / Lab Session Time/Locat... (Text and media area)
- Slides: Datapath - Mandelbrot Lab & Fixed-Point Arithmetic (File)
- Recording (2021 - outdated): Datapath - Mandelbrot & Fixed-Point (URL)
- Lab Session 8 (Text and media area)
- DSD-Lab8_mandelbrot - PDF (File)
- DSD-Lab8_mandelbrot - ZIP (File)
- Wednesday, 13.12.: Lab Session (Project) Time/Loca... (Text and media area)
- Semester & Master Thesis Projects in TCL - 2025 (File)
- Wednesday, 20.12.: Lab Session (Project) Time/Loca... (Text and media area)
- Final project hand in (Text and media area)
15 January - 21 January
Misc
VHDL (Vachoux)
Here are all the documents related to the VHDL part of the course.
Theory (Burg)
Here are all the documents related to the theory part of the course.
Final examination
The final examination will be on Wednesday January 17, 2023, 15h15-18:15h in room CO 260 (CO5/CO6).
We'll first proceed to an identity check, so please bring your CAMIPRO card and have it available at your place.
The examination includes 2 parts: a quiz with 16 questions and problems. The quiz and the problems will be available at the examination session.
The quiz may be only open from a browser running on the server selsrv1 or selsrv2.
The quiz will be open first for a duration of 30 minutes. A maximum of 2 attempts for answering the questions will be possible. The best score from the two attempts will be used. More details on the quiz are available when clicking on the Final quiz link below. A test quiz is provided to let you exercise how a quiz works in Moodle. Note that the actual quiz conditions will be slightly different for the real final quiz.
Then, the problems will have to be solved for the remaining time. They will address two groups of tasks. One group will deal with Prof.Burg's part and will require to deliver results on paper sheets. The other group will deal with the VHDL part and will require to use the computers and the same environment as for the midterm work.
It is very important that you have previously checked that the computer, your dsdusX account on the virtual linux machine and all the tools are working properly before the exam starts. Please announce any issue before the exam day.
You may use any documentation you brought with you or accessed from the Net. Note, however, that you are not allowed to use any email, instant messaging tool or SMS during the examination. Also, the use of personal laptop or USB keys is forbidden. In case you are caught using these or other communication means, your final examination will be graded 0.