Lab in advanced VLSI design

This site includes information and material related to the lab. The content will be updated throughout the semester.

Introduction to Course and Lab Session with Tutorial on Dynamic Logic

• Course overview

• Schedule

• Distribution of the Introductory Laboratory Material  based on Dynamic Logic

Room : CM 1111 

Time : Tuesday 18th , 2:15PM

Lecture and Continuation of the Introductory Tutorial  

• Introductory lecture on fast adders
• Continuation (finish) the tutorial on dynamic logic -> CHECKPOINT

• Lecture: Project Assignment (with explanation Radix & Sparsity for Kogge Stone)
• Design of the G-P Generation Block 
• Design of the 4 Bit Carry Select Adder (Schematics/Simulation)

Finalize Design of Components & Start Top Level Schematic

• D-Flip Flop Design

• Top-level: 64 Bit Parallel Prefix Adder, combining all blocks of the adder (PG Generator, Carry Merge, CSAs)

• The tester is available as part of the package you downloaded at the beginning of the class. As a library in your virtuoso library manager.

Top-level schematic integration

• Lecture: Clock Tree and Floorplan
• Top-level design: Combining all Blocks & Clock Tree

• Optimization of the overall design (transistor sizing)
• Toplevel verification with provided tester

• Midterm Presentation (graded): toplevel verified (frontend only)
• Initial high-level floorplan

• Discussion and Refinement of Floorplan with the TAs
• Check point: floorplan completed

• Start with Layout

• start simple, blocks per blocks. from little to big. start from your floorplan and signal direction chart, to know where the input/output shall be.
  
• run DRC as often as you can. and run it for each level of hierarchy. be careful with the interface with the neighbors blocks
  
• run the LVS for each level of hierarchy - so that you can make sure that each block has been independently validated
  
• do not run PEX simulations for each block. this is not worth your time