Fundamentals of analog VLSI design

EE-424

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Welcome to the course on Fundamentals of Analog & Mixed Signal VLSI Design

Summary

This course provides the stepping stones to becoming an analog IC designer, from simply understanding the operation of a transistor in a simple circuit context. Students must be familiar with basic transistor/circuit concepts to be introduced to more advanced concepts of analog circuit design spanning across devices, structures, and architectures. The course significantly expands on basic concepts of analog circuit design and introduces fundamentals of device modeling, noise, mismatch. It presents a clear design methodology based on the concept of inversion coefficient. It emphasizes the aspect of low-power consumption and design based on figures-of-merit. It also covers widely-used functional circuit blocks and their design considerations.

Coursebook

You can find more information about this course by looking at the course book.

Program

Week Schedule Topics Teacher
1 10.09.2025 Introduction
Technology roadmap
Prof. Enz
2 17.09.2025 Modeling of the MOS transistor for low-power design (long-channel)
Prof. Enz
3 24.09.2025 Modeling of the MOS transistor for low-power design (short-channel)
Prof. Enz
4 01.10.2025 Noise in circuits and systemsProf. Enz
5 08.10.2025 The concept of inversion coefficient and Gm/ID design methodology
Prof. Enz 
6 15.10.2025 Basic building blocks
Prof. Enz 
7 29.10.2025 Amplifiers (OTAs and OPAMPs) Part 1
Prof. Enz
8 05.11.2025 Amplifiers (OTAs and OPAMPs) Part 2
Prof. Enz
9 12.11.2025Offset and 1/f noise reduction techniques
Prof. Enz
10 19.11.2025 Continuous-time filters (CTFs)Prof. Enz
11 26.11.2025 Switched-capacitors filters (SCF)
Prof. Enz
12 03.12.2025 Reference circuits
Prof. Enz
13 10.12.2025Oscillators
Prof. Enz
14 17.12.2025 Comparators
Prof. Enz

* Program may change depending on the process of the semester.

Course schedule and timing (Autumn Semester 2025)

This course will be given every Wednesday from 13:15 to 17:00 in room INF 119. We won't be providing a Zoom link or a lecture recording, so in-person participation in the lecture is highly encouraged. Typically, the lectures will comprise 2 hours of lecture and 2 hours (or less) of exercise/Q&A. Some weeks will include 3 hours of lecture and 1 hour of exercise/Q&A. 

Exercise / Q&A session

Exercises will be given out as homework, where a solution/Q&A session will be held during the exercise session of the following week which require you to use Jupiter or Quarto Notebooks. During the exercise sessions, the professor and the TAs will be present to answer all your questions, so come prepared.

Note, please follow the installation procedure below (in 'additional resources' section) to set up Jupiter and Quarto Notebooks.

Final exam Q&A session

A Q&A session will be scheduled in January, 2026. Exact time and location TBD.

Final Exam

The exam is a written open book exam. You can bring a paper/electronic copy of all the slides and exercises (problems and solutions). Please also bring a pen, paper (plenty!) and a calculator. Also, you must bring a laptop or a tablet to access the exam in Moodle. Thus, connected electronic devices are allowed; however, communication apps and ChatGPT are strictly prohibited. The exam will be in MCQ format, and it will be similar to the exercises given during the semester (but would involve a bit more mathematical rigor).



Additional resources

Books

Device modeling:

[2] Y. Tsividis and C. Mc Andrew, Operation and Modeling of the MOS Transistor, 3rd ed., Oxford University Press, 2001.

CMOS analog IC design:
[3] T. C. Carusone, D. A. Johns, K. W. Martin, Analog Integrated Circuit Design, 2nd edition, Wiley, 2012.
[4] B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., Mc Graw Hill, 2017.
[5]  W. Sansen, Analog Design Essentials, Springer, 2013.
[6] A. Sedra, K. Smith, Microelectronic Circuits, 7th edition, Oxford University Press, 2015.

[7] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley, 2009.

Gm/ID design methodology:
[8] David Binkley, Tradeoffs and Optimization in Analog CMOS Design, Wiley, 2008.

Tools

Jupyter and Quarto notebooks

The solutions to many exercises will be given in the form a Jupyter or Quarto notebook. We are running Jupyter and Quarto notebooks in Visual Studio Code. Please follow the Jupyter and Quarto installation instructions given in my GitHub Analog Circuit Design repository.

Simulations

The designs are validated with the ngspice (version 4.3) circuit simulator and the EKV 2.6 compact model. Please carefully follow the ngspice installation instructions given in my GitHub Analog Circuit Design repository.

Schematic capture

qucs-s
In many examples the circuit are sufficiently simple for the spice schematic to be entered by hand. However you can also use qucs-s to enter the schematic, perform the simulation and plot various curves.
LTSpice

You can also use LTSpice which includes the EKV v2.6 compact model. However, the thermal noise model is wrong and therefore we prefer using qucs-s. The SC filters are simulated in LTSpice with my special library.

There are plenty of introductions and tutorials Additional on LTSpice. Here are a few ones:
Additional documentation on SPICE:


Check your ngspice, qucs and Smash installations

This sections provides examples that will help you checking whether your ngspice, qucs-s and Smash installations work correctly.

The first zip file is a Jupyter Notebook which basically compares the I-V characteristics of nMOS and pMOS obtained from ngspice to those obtained from Smash using the EKV 2.6 compact model for a generic 180nm bulk CMOS process. It also includes a section on noise.

The second zip file is a qucs-s schematic example that plots various characteristics including ID-VG, Gm-VG, ID-VD and Gds-VD characteristics, of nMOS and pMOS transistors from 180nm generic bulk CMOS process. The simulations are ran with ngspice and plotted within qucs-s. You need therefore to have ngspice correctly installed.


EKV Normalized Functions

The files below give you all the EKV normalized functions that are used for the design of low-power analog circuits using the Gm/ID approach using the inversion coefficient. You will find the pdf file and the quarto notebook. The python implementation of the EKV normalized functions is found in the ekv_functions.py file.


Final Exam 2025


1) Introduction (10.09.2025)

Contents:

  • Course description
  • What is circuit design
  • Technology roadmap

Slides:



2) Modeling of the MOS transistor for low-power design (long-channel) (17.09.2025)

Contents:

  • Introduction
  • The static model
  • The small-signal model
  • The noise model
  • Transistor matching

Slides:




3) Modeling of the MOS transistor for low-power design (short-channel) (25.09.2025)

Contents:

  • Introduction
  • Velocity saturation (VS)
  • Channel length modulation (CLM)
  • Drain-induced barrier lowering (DIBL)
  • Output conductance in saturation
  • Impact of short-channel effects on thermal noise
  • The simplified EKV model

Slides:



4) Noise in circuits and systems (1.10.2025)

Contents:

  • Introduction
  • Random signals and noise
  • Main noise sources of circuit components
  • Noise models of basic components
  • Noise calculation in continuous-time (CT) circuits
  • Summary

Slides:



5) The concept of inversion coefficient and Gm/ID design methodology (8.10.2025)

Contents:

  • Introduction
  • The concept of inversion coefficient
  • CS optimization in open-loop configuration
  • CS optimization in closed-loop configuration
  • Figures-of-merit (FoMs) as design guidelines
  • Conclusion

Slides:


6) Basic building blocks (15.10.2025)

Contents

  • Current mirrors
  • Cascode stage
  • Differential pair
  • Elementary gain cells and source follower
  • Current references



7) Amplifiers (OTAs and OPAMPs) (5.11.2025 and 12.11.2025)

Contents

  • Introduction
  • OTA with capacitive feedback
  • The simple OTA
  • The symmetrical OTA


8) Amplifiers (OTAs and OPAMPs) (19.11.2025)

Contents

  • The two-stage OTA or Miller OTA
  • The telescopic OTA
  • The folded cascode OTA
  • The CMOS inverter OTA
  • Improved slew-rate OTAs


9) Offset and 1/f noise reduction techniques (26.11.2025)

Contents:

  • Introduction
  • Noise sampling
  • The autozero (AZ) technique
  • The chopper stabilization (CS) technique
  • Conclusion


10) Continuous-time filters (CTFs) (03.12.2025)

Contents:

  • Introduction
  • RC-active filters
  • MOSFET-C filters
  • Gm-C filters
  • Source-follower CTFs
  • Noise in CTFs
  • Automatic tuning



11) Switched-capacitors circuits and filters (SCF) (10.12.2025)

Contents:

  • Introduction
  • Basic principles
  • Non-ideal effects in SC circuits
  • The design of switched-capacitor filters (SCF)


12) Reference circuits (3.12.2025)


13) Oscillators (10.12.2025)

Contents:

  • Introduction
  • General considerations
  • The 3-points oscillator
  • The cross-coupled pair oscillator



14) Comparators (18.12.2024)


Exercise 1 (17.09.2025)


Exercise 2 (24.09.2025)


Exercise 3 (1.10.2025)


Exercise 4 (8.10.2025)


Exercise 5 (15.10.2025)


Exercise 6 (29.10.2025)


Exercise 7 (5.11.2025)


Exercise 8 (12.11.2025)


Exercise 9 (19.11.2025)


Exercise 10 (26.11.2025)


Exercise 11 (3.12.2025)


Exercise 12 (10.12.2025)


Exercise 13 (17.12.2025)


Mock-up Exam


Final Exam 2024