Lab on hardware-software digital systems codesign

This TP complements previous courses on digital systems design by presenting the complete design of complex systems-on-chip (SoC) that run on Linux with Xilinx FPGAs. We explore high-level synthesis (HLS) as a mechanism to improve productivity in the design of HW.

The complete set of sessions will be given in the lab ELG 022 on Thursdays from 14:15 to 17:00.

Introduction to course format and planning.

The structure of the course and evaluation is presented.

Concept of HW-SW co-design for SoC.

Processor access to peripherals and buses. Types of peripherals. Flow of computation in a SoC with accelerators. Example of SoC: Zynq-7000.

Exercises.

Setting up Linux on the Pynq board. Basic peripherals in a SoC.

Design exploration & optimization using HLS

Synthesis flow.
HLS scheduler.
Loop optimizations.

Array optimizations in HLS
Types of storage resources.
Array optimizations: partitioning & reshaping.
Combining loop & array optimizations.

Cache coherence & virtual memory
Introduction to the concept of virtual memory (VM) and address space protection.
Accessing peripheral registers with MMIO from the address space of a user-level Linux application.
Why memory hierarchies?
Allocating memory suitable for direct memory access (DMA) by peripherals.

Interrupts and Linux device drivers

Exercises
Device drivers for FPGA AXI peripherals in Linux

Memory hierarchies. Caches and buses.

Dynamic job scheduling across multiple accelerators.

Explanation and discussion of final project.

EASTER BREAK

Work on the final project.

Work on the final project.

FINAL PROJECT PRESENTATIONS