Advanced computer architecture
CS-470
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Forum
Slides, Videos, and Documents
- Introduction (Text and media area)
- Schedule (File)
- Practicalities (slides will be available after the... (Text and media area)
- Practicalities (File)
- Part I: General Purpose Architectures (Text and media area)
- Exploiting ILP Dynamically (File)
- Pipelining (Text and media area)
- Pipelining (video) (URL)
- Slides from course CS-200, possibly useful to refresh the background (File)
- Superscalar Out-of-Order Architectures (Text and media area)
- Dynamic Scheduling (video) (URL)
- J. E. Smith and A. R. Pleszkun, Implementation of Precise Interrupts in Pipelined Processors, IEEE Transactions on Computers, 1988 (File)
- Register Renaming (Text and media area)
- Renaming Registers (video) (URL)
- D. Sima, The Design Space of Register Renaming Techniques, IEEE Micro, 2000 (File)
- K. C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, 1996 [This paper is required for Homework Set #1 and for Lab 1] (File)
- Prediction and Speculation (Text and media area)
- Prediction and Speculation (video) (URL)
- J. E. Smith, A Study of Branch Prediction Strategies, International Symposium on Computer Architecture, 1981 (File)
- Simultaneous Multithreading (Text and media area)
- Simultaneous Multithreading (video) (URL)
- D. M. Tullsen et al., Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, International Symposium on Computer Architecture, 1996 (File)
- H. Marr et al., Hyper-Threading Technology Architecture and Microarchitecture, Intel Technology Journal, Q1, 2002 (File)
- Exploiting ILP Statically (Text and media area)
- Exploiting ILP Statically (File)
- VLIW Architectures and Compilers (video) (URL)
- M. S. Schlansker et al., Achieving Complexity, HP Labs Technical Report HPL, 1994 (File)
- J. Huck et al., Introducing the IA-64 Architecture, IEEE Micro, 2000 [This paper is required for Homework Set #2 and for Lab 2] (File)
- H. Sharangpani and K. Arora, Itanium Processor Microarchitecture, IEEE Micro, 2000 [This paper is required for Homework Set #2 and for Lab 2] (File)
- J. Bharadwaj, The Intel IA-64 Compiler Code Generator, IEEE Micro, 2000 [This paper is required for Homework Set #2 and for Lab 2] (File)
- B. R. Rau et al., Code Generation Schema for Modulo Scheduled Loops, International Symposium on Microarchitecture, 1992 (File)
- Dynamic Binary Translation (Text and media area)
- Dynamic Binary Translation (File)
- Dynamic Binary Translation (video) (URL)
- E. Altman et al., Advances and Future Challenges in Binary Translation and Optimization, Proceeedings of the IEEE, 2001 (File)
- V. Bala et al., Dynamo: A Transparent Dynamic Optimization System, Programming Language Design and Implementation, 2000 (File)
- L. Gwennap, Nvidia's First CPU Is a Winner, Microprocessor Report, August 2014 (File)
- For those who are curious: Crusoe Exposed: Re... (Text and media area)
- Part II: Application-Specific Computing (Text and media area)
- Instruction Set Extensions and High-Level Synthesis (File)
- Instruction Set Extensions and High-Level Synthesis (video) (URL)
- Instruction Set Extensions (Text and media area)
- J. A. Fisher, Customized Instruction-Sets for Embedded Processors, Design Automation Conference, 1999 (File)
- Statically Scheduled High-Level Synthesis (Text and media area)
- G. Martin and G. Smith, High-Level Synthesis: Past, Present, and Future, IEEE Design & Test of Computers, 2009 (File)
- J. Cong and Z. Zhang, An efficient and versatile Scheduling algorithm based on SDC formulation, Design Automation Conference, 2006 (File)
- R. Kastner et al., Parallel Programming for FPGAs (URL)
- Dynamically Scheduled High Level Synthesis (Text and media area)
- L. Josipović et al., Dynamically Scheduled High-level Synthesis, International Symposium on Field-Programmable Gate Arrays, 2018 (File)
- L. Josipović et al., An Out-of-Order Load-Store Queue for Spatial Computing, ACM Transactions on Embedded Computing Systems, 2017 (File)
- L. Josipović et al., Speculative Dataflow Circuits, International Symposium on Field-Programmable Gate Arrays, 2019 (File)
- Challenges of High-Level Synthesis (Text and media area)
- Challenges of High-Level Synthesis (File)
- Challenges of High-Level Synthesis (video) (URL)
- T. Ham et al., Decoupling data supply from computation for latency-tolerant communication in heterogeneous architectures, ACM Transactions on Architecture and Code Optimization, June 2017 (File)
- T. Chen and G. E. Suh, Efficient data supply for hardware accelerators with prefetching and access/execute decoupling, IEEE/ACM International Symposium on Microarchitecture, October 2016 (File)
- M. Tan et al., Multithreaded pipeline synthesis for data-parallel kernels, International Conference on Computer-Aided Design, November 2014 (File)
- M. Tan et al., ElasticFlow: A complexity-effective approach for pipelining irregular loop nests, International Conference on Computer-Aided Design, November 2015 (File)
- R. Halstead and W. Najjar, Compiled multithreaded data paths on FPGAs for dynamic workloads, International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, September 2013 (File)
- Part III: Hardware Security (Text and media area)
- Microarchitectural Side‐Channel Attacks (Text and media area)
- Microarchitectural Side‐Channel Attacks (File)
- Microarchitectural Side‐Channel Attacks (video) (URL)
- M. Seaborn and T. Dullien, Exploiting the DRAM RowHammer Bug to Gain Kernel Privileges, Black Hat USA, August 2015 (File)
- D. A. Osvik et al., Cache Attacks and Countermeasures: the Case of AES, CT-RSA, February 2006 (File)
- Y. Yarom and K. Falkner, FLUSH+RELOAD: a High Resolution, Low Noise, L3 Cache Side-Channel Attack, USENIX Security, August 2014 (File)
- G. Irazoqui et al., S$A: A Shared Cache Attack that Works Across Cores and Defies VM Sandboxing—and its Application to AES, IEEE S&P, May 2015 (File)
- M. Lipp et al., Meltdown: Reading Kernel Memory from User Space, USENIX Security, August 2018 (File)
- P. Kocher et al., Spectre Attacks: Exploiting Speculative Execution, IEEE S&P, May 2019 (File)
- Trusted Execution Environments (Text and media area)
- Trusted Execution Environments (File)
- Trusted Execution Environments (video) (URL)
- Physical Side‐Channel Attacks (Text and media area)
- Physical Side‐Channel Attacks (File)
- Physical Side‐Channel Attacks (video) (URL)
- F.-X. Standaert, Introduction to Side-Channel Attacks, in Secure Integrated Circuits and Systems, Springer, 2010 (File)
- P. Kocher, J. Jaffe, B. Jun, Differential Power Analysis, Crypto, August 1999 (File)
Exam
- Example of Exam Paper (File)
- Room and Seating Assignment (File)
- INM 200 Seating Plan (File)
- INM 202 Seatin Plan (File)
Labs
- Lab 1 (Text and media area)
- Lab 1 R10000 (File)
- Lab 1 Slides (File)
- Lab 1 Slides (Solutions) (File)
- K. C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, 1996 (File)
- Simulation Spreadsheet (File)
- Simulation Spreadsheet Solution (File)
- Lab 2 (Text and media area)
- Lab 2 IA-64 (File)
- J. Huck et al., Introducing the IA-64 Architecture, IEEE Micro, 2000 (File)
- J. Bharadwaj, The Intel IA-64 Compiler Code Generator, IEEE Micro, 2000 (File)
- H. Sharangpani and K. Arora, Itanium Processor Microarchitecture, IEEE Micro, 2000 (File)
- Itanium Architecture Software Developer’s Manual Volume 1 (File)
- Itanium Architecture Software Developer’s Manual Volume 3 (File)
- Itanium Software Conventions and Runtime Architecture Guide (File)
- Lab 2 - Solution (File)
- Lab 3 (Text and media area)
- Lab3 Vivado HLS (File)
- Lab3-Material (Folder)
- Xilinx Vivado HLS User Guide (File)
- Xilinx Vivado HLS Tutorial (File)
- Vivado Virtual Machine (URL)
- Lab 4 (Text and media area)
- Lab4 Cache Attack (File)
- Lab4 Material (Folder)
- solution.c (File)