Fundamentals of digital systems
CS-173
[Thursday] Exercises - Digital Design with Verilog - Additional resources
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Description
Additional resources for the exercise session:
- structural_example.v
Verilog file describing the simple combinational circuit in Fig. 1 - structural_example_tb.v
Testbench file to simulate the circuit mentioned above - full_adder1_tb.v
Testbench to simulate the operation of the first Full-Adder variant - full_adder2_tb.v
Testbench to simulate the operation of the second Full-Adder variant - mux_2to1_tb.v
Testbench to simulate the operation of the 2-to-1 MUX - mux_8to1_tb.v
Testbench to simulate the operation of the 8-to-1 MUX