Fundamentals of Analog VLSI Design
Exercise 8 - Solution

Design of the Simple OTA

1 Introduction

Figure 1: Schematic of the simple differential OTA.

Note

Note that all nMOS transistors in Figure 1 have an odd number and all the pMOS transistors an even number which explains the numbering process.

This notebook presents the analysis, design and simulation of the simple 5 transistors OTA presented in Figure 1. We can distinguish the case where M_1a-M_1b are in the common substrate (Figure 1 a) and the case where M_1a-M_1b are in a separate well (Figure 1 b). We will see below that in fully differential mode the effects of the source transconductances on the common substrate schematic are actually canceled. The design phase is using the sEKV model and the inversion coefficient approach [1], [2], [3].

The simple OTA is the simplest single-stage differential OTA having the dominant pole set by the load capacitance. We will see below that in differential mode the effects of the source transconductances on the common source node voltage are actually canceled. In order to minimize the \(V_{GS}\) voltage of M_1a-M_1b, we have chosen to put M_1a-M_1b in a separate well at the cost of a larger area.

We will start with a detailed analysis of the OTA which will allow to derive all the design equations that will be used in the design phase. The OTA is then designed for a given set of specifications for a generic 180 nm bulk CMOS technology. The design is then validated by simulations with ngspice [4] using the EKV 2.6 compact model [5] [6] [7] with parameters corresponding to a generic 180 nm bulk CMOS technology [8] [9].

We now start with the small-signal analysis.

This notebook presents the design of the simple differential OTA shown in Figure 1. We can distinguish the case where M_1a-M_1b are in the common substrate (Figure 1 a) and the case where M_1a-M_1b are in a separate well (Figure 1 b). We will see below that in fully differential mode the effects of the source transconductances on the common substrate schematic are actually canceled.

We will design the circuit with M_1a-M_1b in a separate well for the specifications given below. In this example, we don’t give any specification on the slew-rate (SR). However the sew-rate specification can determine a bias current that is way above the one derived in this example ignoring the SR. If the SR is too high, we can move to adaptive biasing OTAs.

2 Analysis

2.1 Large-signal Analysis

2.1.1 Voltage Transfer Characteristic

Since there are two input terminals, several large-signal voltage transfer characteristics can be derived. In many situations, one of the two input terminals will be maintained at a constant common mode voltage (typically \(V_{DD}/2\)) while the other is connected to some feedback network. If for example the negative input is set constant, at for example the middle of the supply voltage \(V_{DD}/2\), the positive input can be swept from ground to \(V_{DD}\). The output voltage will change from ground to \(V_{DD}\) as well. The amplifier will provide some gain for \(V_{in+}\) ranging close to \(V_{in-}\). Outside this high gain region, the output voltage will saturate either to \(V_{DD}\) for \(V_{in+}\) larger than \(V_{in-}\), or to 0 for \(V_{in+}\) smaller than \(V_{in-}\). Under the above conditions, the maximum output voltage \(V_{out,max}\) in the linear range is limited by M_2b going out of saturation \[\begin{equation} V_{out,max} = V_{DD} - V_{SDsat2b}. \end{equation}\] On the other hand, the minimum output voltage \(V_{out,min}\) of the linear range is limited by M_1b going out of saturation and depends linearly on the common-mode voltage set on \(V_{in-}\) according to \[\begin{equation} V_{out,min} = V_{DSsat1b} - V_{GS1b} + V_{in-}. \end{equation}\] If M_1b is biased in weak inversion then \(V_{DSsat1b} \cong 4 U_T \cong 100\,mV\). The value of \(V_{GS1b}\) depends wether M_1a-M_1b are in a separate well or are in the common substrate. The gate-to-source voltage of a transistor can be expressed from the pinch-off voltage given by \[\begin{equation} V_P-V_S \cong \frac{V_G-V_{T0}}{n} - V_S, \end{equation}\] from which we get \[\begin{equation} V_G = V_{T0} + n V_S + n\,U_T\,(v_p-v_s) \end{equation}\] where the normalized saturation voltage \(v_p-v_s\) can be expressed in terms of the inversion coefficient as \[\begin{equation} v_p-v_s = \ln\left(\sqrt{4 IC+1}-1\right) + \sqrt{4 IC+1} - 1 - \ln(2). \end{equation}\] The gate-to-source voltage is then given by \[\begin{equation} V_{GS} \cong V_{T0} + (n-1)\,V_S + n\,U_T\,(v_p-v_s). \end{equation}\]

\(v_p-v_s\) is equal to zero for \(IC =\) 0.608 and the normalized saturation voltage \(v_p-v_s\) for \(IC=0.1\) is equal to -2.207 times \(n\,U_T\). So in the lower part of moderate inversion and upper part of weak inversion we can approximate \(v_p-v_s \cong 0\) and the gate-to-source voltage can be approximated by \[\begin{equation}\label{eqn:vgs} V_{GS} \cong V_{T0} + (n-1)\,V_S. \end{equation}\]

In case the transistor is in a separate well then \(V_S=0\), the gate-to-source voltage can simply be approximated by the threshold voltage \[\begin{equation} V_{GS} \cong V_{T0}. \end{equation}\]

In case the transistor is in the common substrate, we need to know the source voltage \(V_S\) to estimate the gate-to-source voltage according to \(\eqref{eqn:vgs}\).

M_1a-M_1b in a separate well:

In the case M_1a-M_1b are in a separate well, then \(V_{S1} = 0\). If additionally, M_1a-M_1b are biased in weak inversion then \(V_{DSsat1b} \cong 4 U_T\) and \(V_{GS1b} \cong V_{T0n}\). The minimum output voltage in the linear range is then given by \[\begin{equation} V_{out,min} = 4 U_T - V_{T0n} + V_{in-}. \end{equation}\] As long as M_2b remains in saturation (i.e. for \(V_{out} < V_{out,max}\)), the currents flowing in M_1a and M_1b are imposed equal by the current mirror. When decreasing \(V_{in+}\) and for \(V_{out}\) below \(V_{out,min}\), the current in M_1b is equal to \(I_b/2\) as long as M_1b remains in saturation. The gate voltage of M_1b is equal to \(V_{in-}\) and the source voltage of M_1a and M_1b follows \(V_{in+}\) with a shift of \(V_{GS1a} \cong V_{T0n}\). Since the current is imposed equal to \(I_b/2\) by the current mirror, the decrease of the source voltage increases the gate-to-source voltage of M_1b which has to be compensated by a decrease of the drain-to-source voltage, which is the only remaining degree of freedom in M_1b, to maintain the current constant at \(I_b/2\). This decrease of the drain-to-source voltage of M_1b brings it in the linear region with a drain-to-source voltage close to zero. In such condition, the output voltage is about equal to the source voltage which decreases linearly with the positive input voltage \[\begin{equation} V_{out} \cong V_S = V(1) = V_{in+} - V_{GS1a} \cong V_{in+} - V_{T0n}. \end{equation}\] These considerations lead to the large-signal characteristic shown in Figure 2 which is obtained from simulation in the case of a 0.18~\(\mu\)m process with \(V_{DD}=1.8\,V\).

Figure 2: Large-signal \(V_{out}\) versus \(V_{in+}\) voltage transfer characteristic for various values of the negative input \(V_{in-}\) (M_1a-M_1b in separate well).

M_1a-M_1b in the common substrate:

In the case M_1a-M_1b are in the common substrate, the gate-to-source voltage of M_1b will depend on the source voltage \(V_S\). For M_1a-M_1b biased in weak inversion we have \[\begin{equation} V_{GS1b} \cong V_{T0n} + (n_{1b}-1) V_S. \end{equation}\] The source voltage is also given by \[\begin{equation} V_S = -V_{GS1b} + V_{in-} \cong - V_{T0n} - (n_{1b}-1) V_S + V_{in-} \end{equation}\] from which we can deduce \(V_S\) as \[\begin{equation} V_S \cong \frac{V_{in-}-V_{T0n}}{n_{1b}}. \end{equation}\] The gate-to-source voltage of M_1b then writes \[\begin{equation} V_{GS1b} \cong V_{in-} - \frac{V_{in-}-V_{T0n}}{n_{1b}} \end{equation}\] Finally, the minimum output voltage is given by \[\begin{equation} V_{out,min} \cong V_{in-} + 4 U_T - V_{GS1b} = \frac{V_{in-}-V_{T0n}}{n_{1b}} + 4 U_T. \end{equation}\] Below \(V_{out,min}\), the output voltage will decrease linearly with \(V_{in+}\) with a slope \(1/n_{1a}\) \[\begin{equation} V_{out} \cong \frac{V_{in+}-V_{T0n}}{n_{1a}}. \end{equation}\] This is confirmed by the simulations results shown in Figure 3.

Figure 3: Large-signal \(V_{out}\) versus \(V_{in+}\) voltage transfer characteristic for various values of the negative input \(V_{in-}\) (M_1a-M_1b in common substrate).

2.1.2 Input Common Mode Voltage Range

The minimum common mode input voltage \(V_{ic,min}\) is given by the saturation limit of M_3b \[\begin{equation} V_{ic,min} = V_{GS1} + V_{DSsat3b}. \end{equation}\] The maximum common mode input voltage \(V_{ic,max}\) is given by the limit of saturation of M_1a \[\begin{equation} V_{ic,max} = V_{GS1a} - V_{DSsat1a} - V_{SG2} + V_{DD} \cong V_{GS1a}- 4 U_T - V_{SG2} + V_{DD}. \end{equation}\] The gate-to-source voltage of M_1a \(V_{GS1}\) depends whether M_1a-M_1b are in a separate well or in the common substrate.

M_1a-M_1b in a separate well:

In the case M_1a-M_1b are biased in weak inversion and are in a separate well, \(V_{GS1} \cong V_{T0n}\), and the common mode input voltage limits are given by \[\begin{align} V_{ic,min} &\cong V_{T0n} + V_{DSsat3b}\\ V_{ic,max} &\cong V_{T0n} - 4 U_T - V_{SG2} + V_{DD}. \end{align}\] The common mode input voltage range \(\Delta V_{ic}\) is then given by \[\begin{equation}\label{eqn:delta_vic_well} \Delta V_{ic} \triangleq V_{ic,max} - V_{ic,min} \cong V_{DD} - V_{SG2} - 4 U_T - V_{DSsat3b}. \end{equation}\] Equation \(\eqref{eqn:delta_vic_well}\) shows that although it is appropriate to bias M_2a-M_2b and M_3a-M_3b in strong inversion, choosing a too large saturation voltage will reduce the available common mode input range.

M_1a-M_1b in a common substrate:

In the case M_1a-M_1b are biased in weak inversion and are in a common substrate, the gate-to-source voltage of M₁ is given by \[\begin{equation}\label{eqn:VGS1_VS} V_{GS1} \cong V_{T0n} + (n_1-1) \cdot V_S \end{equation}\] For \(V_{ic}=V_{ic,min}\), \(V_S=V_{DSsat3b}\) and \[\begin{equation} V_{ic,min} = V_{GS1} + V_{DSsat3b} = V_{T0n} + (n_1-1) V_{DSsat3b} + V_{DSsat3b} = V_{T0n} + n_1 V_{DSsat3b}. \end{equation}\] The source voltage for \(V_{ic}=V_{ic,max}\) is equal to \[\begin{equation} V_S \cong V_{ic,max} - V_{GS1} = V_{ic,max} - V_{T0n} - (n_1-1) V_S \end{equation}\] and hence \[\begin{equation} V_S \cong \frac{V_{ic,max} - V_{T0n}}{n_1}. \end{equation}\] Replacing in \(\eqref{eqn:VGS1_VS}\) results in \[\begin{equation} V_{GS1} \cong V_{ic,max} - \frac{V_{ic,max} - V_{T0n}}{n_1} \end{equation}\] and finally \[\begin{equation} V_{ic,max} \cong n_1 (V_{DD} - V_{SG2} - 4 U_T) + V_{T0n}. \end{equation}\] Finally, the common mode input voltage range \(\Delta V_{ic}\) is given by \[\begin{equation}\label{eqn:delta_vic_nowell} \Delta V_{ic} \triangleq V_{ic,max} - V_{ic,min} \cong n_1 (V_{DD} - V_{SG2} - 4 U_T - V_{DSsat3b}). \end{equation}\] From \(\eqref{eqn:delta_vic_well}\) and \(\eqref{eqn:delta_vic_nowell}\), we see that having M_1a-M_1b in the common substrate gives a common mode input voltage range \(n_1\) larger than having them in a separate well. Since the upper limit is identical, it comes from the fact that the slope of the output voltage versus \(V_{in+}\) is \(1/n_1\) which is slightly smaller than \(1\).

2.1.3 Slew-Rate

Assuming that the differential pair is biased in weak inversion, when the magnitude of the differential voltage becomes larger than about \(4 U_T\), the magnitude of the output current saturates to \(I_b\). The OTA then behaves like a current source of value \(I_b\) loaded by the load capacitance \(C_L\). The rate of voltage change across the load capacitance is therefore limited to a maximum given by \[\begin{equation}\label{eqn:sr} SR \triangleq \left|\frac{d V{out}}{dt}\right|_{max} = \left|\frac{I_{out}}{C_L}\right|_{max} = \frac{I_b}{C_L}. \end{equation}\] For a given load capacitance and a given available transient time, \(\eqref{eqn:sr}\) often determines the minimum required bias current.

2.2 Small-signal analysis

The small-signal schematic corresponding to the schematics of Figure 1 are shown in Figure 4.

Figure 4: Small-signal schematic of the simple OTA.

In the case M_1a-M_1b are in the common substrate (left figure), we can recognize the source transconductances in Figure 4 which are controlled by the common voltage at the source \(\Delta V_1\).

We now first look at the operation in differential mode.

2.2.1 Differential mode

In order to derive the differential transadmittance, we first will simplify the small-signal schematic of Figure 4 by considering that the output conductances are much smaller than the transconductances \(G_{ds} \ll G_m < G_{ms}\) for all transistors. This leads to the simplified small-signal schematics shown in Figure 5.

Figure 5: Simplified small-signal schematic.

The differential transadmittance is defined as \[\begin{equation} Y_{md} \triangleq \frac{I_{out}}{V_{id}}, \end{equation}\] where \(V_{id} \triangleq V_{in+}-V_{in-}\) is the input differential voltage and \(I_{out}\) the output current. Note that in the small-signal schematic, the output node has been connected to the ac ground. The output conductance of transistor M_2b \(G_{ds2b}\) is then grounded and can therefore be neglected. Also, the output conductance of transistor M_2a \(G_{ds2a}\) is in parallel with its transconductance \(G_{m2a}\) and since usually \(G_{ds2a} \ll G_{m2a}\), it can also be neglected. Assuming a perfect matching, i.e. \(G_{m1b}=G_{m1a}=G_{m1}\), \(G_{ms1b}=G_{ms1a}=G_{ms1}\) and \(G_{m2b}=G_{m2a}=G_{m2}\), the differential transadmittance is then given by \[\begin{equation}\label{eqn:ymd} Y_{md} = G_{m1} \frac{1+s \tau_2/2}{1+s \tau_2} = G_{m1} \frac{1+s/(2\omega_2)}{1+s/\omega_2} \end{equation}\] where \(\tau_2 = 1/\omega_2 \triangleq C_2/G_{m2}\) is the time constant introduced by the current mirror M_2a-M_2b due to the parasitic capacitance \(C_2\) at node 2. Note that \(\eqref{eqn:ymd}\) is valid for both M_1a-M_1b in a separate well and in a common substrate. This is due to the fact that in differential mode and assuming a perfect matching, the common source node 1 does not change and can be considered as an ac ground. This means that \(\Delta V_1=0\) and hence the two small-signal circuits on the left and right of Figure 5 become identical.

The magnitude of \(Y_{md}\) normalized to the low-frequency value \(G_{m1}\) is plotted versus the frequency in Figure 6.

Figure 6: Magnitude of the transadmittance \(Y_{md}\) normalized to \(G_{m1}\) versus the frequency.

A transfer function like \(\eqref{eqn:ymd}\) is called a pole-zero doublet. This means that the zero, situated at twice the value of the pole, is canceling the effect of the pole at frequencies above the zero. For \(\omega < \omega_2\), both current branches of the differential pair are active. On the other hand, for \(\omega_2 < \omega\), the voltage at node 2 is low-pass filtered and ac grounded and therefore the small-signal current coming from transistor M_1a is not copied to the output anymore. The output current is hence only coming from transistor M_1b, resulting in half the low-frequency transconductance corresponding to the -6 dB asymptote shown in Figure 6.

The differential mode open-loop voltage transfer function \(A_{vd}\) is simply given by \[\begin{equation} A_{vd} \triangleq \frac{\Delta V_{out}}{V_{id}} = Y_{md} \cdot Z_L \end{equation}\] where \(Z_L\) is the output load. In the case the output load is only capacitive we then have \[\begin{equation} Y_L \triangleq 1/Z_L = G_o + s\,C_L \end{equation}\] where \(G_o\) is the total conductance at the output node \(G_o = G_{ds1b} + G_{ds2b}\). This results in \[\begin{equation} A_{vd} = \frac{G_{m1}}{G_o + s C_L} \frac{1+s/(2\omega_2)}{1+s/\omega_2} = A_{dc} \frac{1+s/(2\omega_2)}{(1+s/\omega_0) (1+s/\omega_2)} \end{equation}\] where \(A_{dc} \triangleq G_{m1}/G_o\) is the DC gain, \(\omega_o \triangleq G_o/C_L\) the dominant pole set by the load capacitance \(C_L\) and \(\omega_2 \triangleq G_{m2}/C_2\) the non-dominant due to the parasitic capacitance at the current mirror node 2. The Bode plot of the small-signal differential voltage transfer function is shown in Figure 7.

Figure 7: Magnitude and phase of the open-loop voltage differential gain \(A_{vd}\) normalized to \(G_{m1}\) versus the frequency.

Assuming that the non-dominant pole \(\omega_2\) is much higher than the unity gain frequency \(\omega_u\), the latter is then given by \[\begin{equation} \omega_u = A_{dc} \cdot \omega_0 = \frac{G_{m1}}{G_o} \frac{G_o}{C_L} = \frac{G_{m1}}{C_L}. \end{equation}\] Note that the phase reaches a minimum for \(\omega= \sqrt{2} \, \omega_2\) \[\begin{equation} \Phi_{min} = -\frac{\pi}{2} + arctg(\sqrt{2}/2) - arctg(\sqrt{2}) \cong -109.5^\circ. \end{equation}\]

2.2.2 Common mode

In common mode, the differential voltage is zero \(V_{id}=0\) and both inputs are controlled by the common mode voltage \(V_{ic}\). The common mode transadmittance \(Y_{mc}\) is defined as \[\begin{equation}\label{eqn:Ymc} Y_{mc} \triangleq \frac{I_{out}}{V_{ic}} = -G_{m1} \frac{s^2 \tau_1 \tau_2}{(1+s\tau_1)(1+s\tau_2)} = -G_{m1} \frac{s^2/(\omega_1 \omega_2)}{(1+s/\omega_1)(1+s/\omega_2)} \end{equation}\] where \(\tau_1\) corresponds to the time constant of the common source node 1 of the differential pair given by \[\begin{equation} \tau_1 = \frac{1}{\omega_1} = \frac{C_1}{2 G_{m1}} \end{equation}\] for M_1a-M_1b in a separate well and \[\begin{equation} \tau_1 = \frac{1}{\omega_1} = \frac{C_1}{2 G_{ms1}} = \frac{C_1}{2 n_1 G_{m1}} \end{equation}\] for M_1a-M_1b in a common substrate. \(\tau_2\) corresponds to the time constant of the current mirror node 2 and is given by \[\begin{equation} \tau_2 = \frac{1}{\omega_2} \triangleq \frac{C_2}{G_{m2}}. \end{equation}\]

From \(\eqref{eqn:Ymc}\) we see that \(Y_{mc}\) is zero at low frequency. Note that it is actually limited by the conductance at node 1 \(G_1\) and the mismatch in the differential pair and the current mirror. At high frequency (i.e. \(\omega \gg \omega_1\) and \(\omega \gg \omega_2\)), nodes 1 and 2 are ac grounded and the output current is directly provided by M_1b, so that \(Y_{mc}\) becomes equal to \(-G_{m1}\).

The common-mode rejection ratio (CMMR) is then given by \[\begin{equation} CMRR \triangleq \frac{Y_{md}}{Y_{mc}} = -\frac{(1+s\tau_1)(1+s\tau_2/2)}{s^2\tau_1\tau_2} = -\frac{(1+s/\omega_1)(1+s/(2\omega_2)}{s^2/(\omega_1\omega_2)}, \end{equation}\] which, assuming a perfect matching, is ideally infinite at low frequency and degrades for increasing frequency to reach -6dB at high frequency.

2.3 Noise Analysis

In order to calculate the noise output current \(I_{nout}\), the input terminals are grounded. The small-signal equivalent circuit including the noise sources of all the transistors are shown in Figure 8.

Figure 8: Simplified small-signal noise schematic. a) M_1a-M_1b in common substrate. b) M_1a-M_1b in separate well.

The left schematic corresponds to M_1a-M_1b in a separate well whereas the right schematic corresponds to all N-channel transistors in the same substrate. Note that all the output conductances have been neglected. Since we want to calculate the noise at low-frequency (meaning for \(\omega < \omega_2\)), we can neglect the parasitic capacitances \(C_1\) and \(C_2\). If a perfect symmetry is assumed, then the two currents generated by transconductances \(G_{m1a}\) and \(G_{m1b}\), or \(G_{ms1a}\) and \(G_{ms1b}\) in the above schematic are equal. If the current mirror is also assumed symmetrical, then the current coming from M_1a is mirrored at the output and compensated by the current coming directly from M_1b. Therefore, the transconductances \(G_{m1a}\) and \(G_{m1b}\) (respectively \(G_{ms1a}\) and \(G_{ms1b}\)) have no effect on the output current. They can therefore be neglected. Assuming again perfect symmetry, the noise currents \(I_{n3a}\) and \(I_{n3b}\) coming from transistors M_3a and M_3b split equally between the two branches and produce no net current at the output neither. They can therefore also be neglected. Finally, the output noise current is simply given by \[\begin{equation}\label{eqn:Inout} I_{nout} = I_{n1a} - I_{n1b} - I_{n2a} + I_{n2b}. \end{equation}\] This means that the transfer functions at low-frequency from each of the noise sources to the output current is simply equal to \(\pm 1\). Note that the sign is of no importance since for noise we are only interested by the square of the magnitude of the transfer functions.

The power spectral density (PSD) of the output noise current is then given by \[\begin{equation} S_{nout}(f) = 4kT \cdot G_{nout}(f), \end{equation}\] with \[\begin{equation} G_{nout}(f) = G_{n1a}(f) + G_{n1b}(f) + G_{n2a}(f) + G_{n2b}(f) = 2(G_{n1}(f) + G_{n2}(f)). \end{equation}\] The noise conductances \(G_{ni}(f)\) with \(i=1,2\), are frequency dependent since they include both the thermal and the 1/f noise. They are given by \[\begin{equation}\label{eqn:gni_def} G_{ni}(f)=\gamma_{ni} \cdot G_{mi} + G_{mi}^2 \cdot \frac{\rho_i}{W_i\,L_i\,f}, \end{equation}\] for \(i=1,2\) where \(\rho_1=\rho_n\) and \(\rho_2=\rho_p\) and \[\begin{equation} \gamma_{ni} = \begin{cases} \frac{n_i}{2} & \textsf{in weak inversion}\\ \frac{2}{3}\,n_i & \textsf{in strong inversion}. \end{cases} \end{equation}\]

The noise can be referred to the differential input by dividing \(G_{nout}\) by \(G_{m1}^2\), resulting in \[\begin{equation} R_{nin}(f) \triangleq \frac{G_{nout}}{G_{m1}^2}= R_{nt} + R_{nf}(f) \end{equation}\] where \(R_{nt}\) is the part of the input-referred noise resistance corresponding to the thermal noise \[\begin{equation}\label{eqn:Rnt} R_{nt} = 2\left(\frac{\gamma_{n1}}{G_{m1}} + \gamma_{n2} \frac{G_{m2}}{G_{m1}^2}\right) = \frac{2 \gamma_{n1}}{G_{m1}} \cdot (1 + \eta_{th}), \end{equation}\] where \[\begin{equation} \eta_{th} = \frac{\gamma_{n2}}{\gamma_{n1}} \frac{G_{m2}}{G_{m1}} \end{equation}\] represents the contribution to the input-referred thermal noise of the current mirror relative to that of the differential pair.

The flicker noise resistance \(R_{nf}(f)\) is the part corresponding to the 1/f noise \[\begin{equation}\label{eqn:Rnf} R_{nf}(f) = 2 \left[\frac{\rho_n}{W_1 L_1 f} + \left(\frac{G_{m2}}{G_{m1}}\right)^2 \frac{\rho_p}{W_2 L_2 f}\right] = \frac{2 \rho_n}{W_1 L_1 f} \cdot (1 + \eta_{fl}). \end{equation}\] where \[\begin{equation} \eta_{fl} = \left(\frac{G_{m2}}{G_{m1}}\right)^2 \frac{\rho_p}{\rho_n} \frac{W_1 L_1}{W_2 L_2} \end{equation}\] represents the contribution to the input-referred flicker noise of the current mirror relative to the differential pair.

In the same way a noise excess factor \(\gamma_n\) has been defined for a single transistor, a thermal noise excess factor can also be defined for the complete OTA as \[\begin{equation}\label{eqn:gamma_ota} \gamma_{ota} \triangleq G_m \cdot R_{nt} = \frac{G_{nout,thermal)}}{G_m} = 2\gamma_{n1} \cdot (1 + \eta_{th}) \end{equation}\] where \(G_m=G_{m1}\) is the OTA differential transconductance. The total input-referred thermal noise resistance then writes \[\begin{equation} R_{nt} = \frac{\gamma_{ota}}{G_{m1}}. \end{equation}\]

The minimum value of the OTA noise excess factor is equal to that of the differential pair only, namely \(\gamma_{ota,min} = 2 \gamma_{n1}\). In order to limit the contribution of the current mirror to a minimum, the second term in the bracket of \(\eqref{eqn:gamma_ota}\) should be made much smaller than one. This can be achieved by setting the transconductance ratio \(G_{m2}/G_{m1} \ll 1\). This can be done by biasing M_1a-M_1b in weak inversion and M2-M_2b in strong inversion, respectively. Replacing \(G_{m2}/G_{m1}\) by \[\begin{equation}\label{eqn:Gm2_over_Gm1} \frac{G_{m2}}{G_{m1}} = \frac{2 n_1 U_T}{n_2 V_{DSsat2}} = \frac{2 n_1 U_T}{n_2 V_{P2}} \cong \frac{2 n_1 U_T}{V_{G2}-V_{TOp}} \end{equation}\] results in \[\begin{equation} \gamma_{ota} = 2\gamma_{n1}\left(1+\frac{\gamma_{n2}}{\gamma_{n1}} \frac{2 n_1 U_T}{V_{G2}-V_{TOp}}\right) = n_1 \left(1+\frac{8 n_2}{3} \frac{U_T}{V_{G2}-V_{TOp}}\right), \end{equation}\] where \(\gamma_{n1}=n_1/2\) and \(\gamma_{n2}=n_2 2/3\). The OTA thermal noise excess factor is therefore minimized by setting the transconductance ratio \(G_{m2}/G_{m1} \ll 1\), which is realized easily if transistors M_1a-M_1b are biased in weak inversion and M2-M_2b in strong inversion and by choosing an overdrive voltage \(V_{G2}-V_{TOp}\) of M2-M_2b much larger than \(8 n_2/3 U_T \cong 4 U_T\) where it has been assumed that \(n_2 \cong 3/2\).

The 1/f noise corner frequency \(f_k\) is defined as the frequency at which the 1/f noise becomes equal to the thermal noise \[\begin{equation} R_{nf}(f_k) = R_{nt} \end{equation}\] and is given by \[\begin{equation} f_k = \frac{G_{m1}}{\gamma_{ota}} \frac{2 \rho_n}{W_1 L_1} \cdot (1 + \eta_{fl}). \end{equation}\]

The corner frequency can be reduced by increasing \(W_1\,L_1\) and \(W_2\,L_2\) at the same time to conserve the same \(\eta_{fl}\) factor. Of course increasing the area of transistors M1 and M2 increases the parasitic capacitance at node 2 and hence decreases the non-dominant pole \(\omega_2\).

2.4 Input-referred offset voltage

Mismatch between the two transistors of the differential pair M_1a-M_1b and of the current mirror M2-M_2b causes some current to flow at the output even for a zero differential input voltage \(V_{id}=0\). This output current can be compensated by applying a certain differential input voltage defined as the input-referred offset voltage \(V_{os}\).

The analysis of the mismatch effects for deriving the variance of the input-referred offset voltage can be done similarly to the noise analysis. We can reuse \(\eqref{eqn:Inout}\) with \[\begin{align} I_{n1a} &= +\frac{\Delta I_{D1}}{2},\\ I_{n1b} &= -\frac{\Delta I_{D1}}{2},\\ I_{n2a} &= -\frac{\Delta I_{D2}}{2},\\ I_{n2b} &= +\frac{\Delta I_{D2}}{2}, \end{align}\] and where \(\Delta I_{D1}\) and \(\Delta I_{D2}\) are the current mismatch in the differential pair and in the current mirror, respectively. The output current due to these current mismatches is then given by \[\begin{equation} I_{out} = \Delta I_{D1} + \Delta I_{D2}. \end{equation}\] Of course \(\Delta I_{D1}\) and \(\Delta I_{D2}\) are random variables. The variance of the offset output current is then given by \[\begin{equation} \sigma_{Iout}^2 = \sigma_{\Delta I_{D1}}^2 + \sigma_{\Delta I_{D2}}^2 = I_b^2 \cdot \left(\sigma_{\Delta I_{D1}/I_{D1}}^2 + \sigma_{\Delta I_{D2}/I_{D2}}^2\right) \end{equation}\] where \[\begin{align} \sigma_{\Delta I_{D1}/I_{D1}}^2 &= \sigma_{\beta 1}^2 + \left(\frac{G_{m1}}{I_b}\right)^2\,\sigma_{VT1}^2,\\ \sigma_{\Delta I_{D2}/I_{D2}}^2 &= \sigma_{\beta 2}^2 + \left(\frac{G_{m2}}{I_b}\right)^2\,\sigma_{VT2}^2. \end{align}\] with \[\begin{align} \sigma_{\beta i}^2 &= \frac{A_{\beta}^2}{W_i L_i},\\ \sigma_{V_{T0i}}^2 &= \frac{A_{VT}^2}{W_i L_i}. \end{align}\] for \(i=1,2\). \(A_{\beta}\) (usually given in %\(\cdot\mu\)m) and \(A_{VT}\) (usually given in mV\(\cdot\mu\)m) are the \(\beta\) and threshold matching parameters for the process to be used.

The variance of the output offset current then writes \[\begin{equation}\label{eqn:Iosout} \sigma_{Iout}^2 = I_b^2 \cdot \left(\sigma_{\beta 1}^2 + \sigma_{\beta 2}^2\right) + G_{m1}^2\;\sigma_{VT1}^2 + G_{m2}^2\;\sigma_{VT2}^2. \end{equation}\]

The variance of the input-referred offset voltage is obtained by dividing the variance of the output offset current \(\eqref{eqn:Iosout}\) by \(G_{m1}^2\) resulting in \[\begin{equation} \sigma_{Vos}^2 = \left(\frac{I_b}{G_{m1}}\right)^2 \left(\sigma_{\beta 1}^2 + \sigma_{\beta 2}^2\right) + \left(\frac{G_{m2}}{G_{m1}}\right)^2 \sigma_{VT2}^2 + \sigma_{VT1}^2. \end{equation}\] which can be written as \[\begin{equation}\label{eqn:sigma_vos} \sigma_{Vos}^2 = \sigma_{VT}^2 + \sigma_{\beta}^2, \end{equation}\] where \(\sigma_{VT}\) is the \(V_T\)-mismatch given by \[\begin{equation}\label{eqn:sigma_vt} \sigma_{VT}^2 = \sigma_{V_{T1}}^2 \cdot (1 + \xi_{V_T}). \end{equation}\] where \(\xi_{V_T}\) represents the \(V_T\)-mismatch contribution to the input-referred offset of the current mirror relative to that of the differential pair \[\begin{equation}\label{eqn:xivt} \xi_{V_T} = \left(\frac{G_{m2}}{G_{m1}}\right)^2 \cdot \frac{\sigma_{V_{T2}}^2}{\sigma_{V_{T1}}^2} = \left(\frac{G_{m2}}{G_{m1}}\right)^2 \cdot \left(\frac{A_{V_{Tp}}}{A_{V_{Tp}}}\right)^2 \cdot \frac{W_1\,L_1}{W_2\,L_2}. \end{equation}\] \(\sigma_{\beta}\) is the \(\beta\)-mismatch given by \[\begin{equation}\label{eqn:sigma_beta} \sigma_{\beta}^2 = \left(\frac{I_b}{G_{m1}}\right)^2 \cdot \sigma_{\beta_1}^2 \cdot (1 + \xi_{\beta}), \end{equation}\] where \(\xi_{\beta}\) represents the \(\beta\)-mismatch contributions to the input-referred offset of the current mirror relative to that of the differential pair \[\begin{equation}\label{eqn:xibeta} \xi_{\beta} = \frac{\sigma_{\beta_2}^2}{\sigma_{\beta_2}^2} = \left(\frac{A_{\beta_p}}{A_{\beta_n}}\right)^2 \cdot \frac{W_1\,L_1}{W_2\,L_2}. \end{equation}\]

From \(\eqref{eqn:sigma_beta}\), we see that the contribution of the \(\beta\) mismatch to the input-referred offset voltage can be minimized by choosing \(I_b/G_{m1}\) as small as possible (or \(G_{m1}/I_b\) as large as possible). This can be done by biasing the transistors of the differential pair in weak inversion. Secondly, from \(\eqref{eqn:xivt}\) we see that the contribution of the \(V_T\) mismatch of the current mirror \(\xi_{V_T}\) an also be minimized by setting \(G_{m2}/G_{m1} \ll 1\). Since M_1a and M_2a (M_1b and M_2b) share the same bias current \(I_{D1}=I_{D2}=I_b\), this can only be done by biasing the current mirror M_2a-M_2b in strong inversion. In this case, the transconductances of M₁ and M₂ are then given by \(G_{m1} = I_b/(n_1 U_T)\) and \(G_{m2} = 2 I_b/(n_2 V_{DSsat2})\) with \(V_{DSsat} = V_{P2}\), leading to \[\begin{equation} \frac{G_{m2}}{G_{m1}} = \frac{2 n_1 U_T}{n_2 V_{DSsat2}} = \frac{2 n_1 U_T}{n_2 V_{P2}} \cong \frac{2 n_1 U_T}{V_{G2}-V_{TOp}} \end{equation}\] The overdrive voltage of M_2a-M_2b \(V_{G2}-V_{TOp}\) has therefore to be chosen much larger than \(2 n_1 U_T\). However, the overdrive voltage \(V_{G2}-V_{TOp}\) cannot be made too large since it will lead to a large \(V_{SG2}\) voltage that, for a given input common mode voltage, will push M_1a out of saturation.

3 Design

3.1 Specifications

The OTA specifications are given in Table 1.

Note

The specifications given in Table 1 are simplified specifications. They are mainly targeting the achievement of a certain gain-bandwidth product \(GBW\) and DC gain at lowest current consumption. The \(GBW\) sets the differential pair transconductance while the DC gain sets the output conductance. There is an additional specification on the random input-referred offset voltage which, if not met, might eventually require to increase the transistors area. There are no specifications on thermal noise since the transconductance is set by the \(GBW\). There are no specifications on the flicker noise but if the corner frequency was set lower this would required to increase the transistors area. There are also no specifications on the slew-rate, which might be small because of the low-power objective. Finally, there are many more specifications such as CMRR, PSRR, input common-mode voltage range, output-voltage swing, etc… that are not discussed in this example.

Table 1: OTA specifications.

Specification	Symbol	Value	Unit
Minimum DC gain	\(A_{{dc}}\)	60	\(dB\)
Minimum gain-bandwidth product	\(GBW\)	10	\(MHz\)
Load capacitance	\(C_L\)	0.1	\(pF\)
Maximum input-referred offset voltage	\(V_{{os,max}}\)	4	\(mV\)

3.2 Process

We will design the simple OTA for a generic 180nm bulk CMOS process. The physical parameters are given in Table 2, the global process parameters in Table 3 and finally the MOSFET parameters in Table 4.

Table 2: Physical parameters

Parameter	Value	Unit
\(T\)	300	\(K\)
\(U_T\)	25.875	\(mV\)

Table 3: Global process parameters

Parameter	Value	Unit
\(V_{DD}\)	1.8	\(V\)
\(C_{ox}\)	8.443	\(\frac{fF}{\mu m^2}\)
\(W_{min}\)	200	\(nm\)
\(L_{min}\)	180	\(nm\)

Table 4: Transistor process parameters

Parameter	NMOS	PMOS	Unit
sEKV parameters
\(n\)	1.27	1.31	-
\(I_{{spec\Box}}\)	715	173	\(nA\)
\(V_{{T0}}\)	0.455	0.445	\(V\)
\(L_{{sat}}\)	26	36	\(nm\)
\(\lambda\)	20	20	\(\frac{{V}}{{\mu m}}\)
Overlap capacitances parameters
\(C_{{GDo}}\)	0.366	0.329	\(\frac{{fF}}{{\mu m}}\)
\(C_{{GSo}}\)	0.366	0.329	\(\frac{{fF}}{{\mu m}}\)
\(C_{{GBo}}\)	0	0	\(\frac{{fF}}{{\mu m}}\)
Junction capacitances parameters
\(C_J\)	1	1.121	\(\frac{{fF}}{{\mu m^2}}\)
\(C_{{JSW}}\)	0.2	0.248	\(\frac{{fF}}{{\mu m}}\)
Flicker noise parameters
\(K_F\)	8.1e-24	6.8e-23	\(J\)
\(AF\)	1	1	-
\(\rho\)	0.05794	0.4828	\(\frac{{V \cdot m^2}}{{A \cdot s}}\)
Matching parameters
\(A_{{VT}}\)	5	5	\(mV \cdot \mu m\)
\(A_{{\beta}}\)	1	1	\(\% \cdot \mu m\)
Source and drain sheet resistance parameter
\(R_{{sh}}\)	600	2386	\(\frac{{\Omega}}{{\mu m}}\)
Width and length parameters
\(\Delta W\)	39	54	\(\,nm\)
\(\Delta L\)	-76	-72	\(\,nm\)

3.3 Design procedure

Important

For this process, the transistor dimensions are rounded to 10nm. We also will ignore the length and width reduction parameters \(DL\) and \(DW\). The main reason is that most of the transistor length and width are sufficiently large that ignoring these parameters has little impact.

3.3.1 Sizing of M_1a-M_1b

M_1a-M_1b are biased in weak inversion in order to

• maximize the \(G_m/I_D\) ratio and
• minimize the input-referred offset.

They are sized according to the specification on the GBW and the load capacitance and the required slew-rate. Recalling that \[\begin{equation} GBW = \frac{G_{m1}}{2 \pi C_{out}}, \end{equation}\] where \(G_{m1}\) is the gate transconductance of M_1a-M_1b and \(C_{out}\) is the total output capacitance which includes the parasitic capacitance and the load capacitance \(C_L\). Since we do not yet know the sizes of M_1a and M_2b, we cannot estimate the total output capacitance. We will start assuming \(C_{out}=C_L\). \(G_{m1}\) is then set by the \(GBW\) as \[\begin{equation} G_{m1} \cong 2 \pi\,GBW\,C_L. \end{equation}\] This gives a required transconductance \(G_{m1} =\) 6.283 \(\mu A/V\). The minimum current to achieve this transcondcutance is obtained in weak inversion where \(G_{m1}\) is given by \[\begin{equation} G_{m1} = \frac{I_b}{n U_T}, \end{equation}\] resulting in a minimum bias current given by \[\begin{equation} I_{b,min} = 2\pi\,n_{0n}\,U_T\,C_L\,GBW. \end{equation}\] For the given specifications we get \(I_{b,min}=\) 207 \(nA\). In order to achieve the high gain-bandwidth product, we have to be particularly careful about the parasitic capacitances at the output and current mirror. Setting the inversion coefficient of M_1a-M_1b too low will lead to a large transistor and hence a large capacitance at the drain of M_1b which adds to the load capacitance. We will choose to bias M_1a-M_1b in moderate iversion with \(IC_1 =\) 1.0. This gives a normalized \(G_m\,n\,U_T/I_D =\) 0.618 and \(I_b =\) 334 \(nA\).

The corresponding slew-rate is then equal to \(SR_{min} =\) 3.344 \(V/\mu s\) which we will consider as sufficient.

Important

If the slew-rate is not sufficient, the bias current \(I_b\) should be increased resulting in a higher current and power consumption. Other options include the use of a class AB OTA [10] or a dynamic/adaptive biasing OTA [11].

To have some margin to account for the additional parasitic capacitance at the output due to the junction capacitances that add to the load capacitance \(C_L\), we set \(I_b =\) 350 \(nA\) and the inversion coefficient to \(IC_1=\) 1.0. The transconductance can be calculated from the \(G_m/I_D\) function as \(G_{m1} =\) 6.576 \(\mu A/V\). This leads to a gain-bandwidth product \(GBW =\) 10.5 \(MHz\), which is slightly higher than the target specification offering some margin.

Knowing the drain current \(I_{D1}\) and the inversion coefficient, we can calculate the \(W/L\) aspect ratio for M_1a-M_1b as \(W_1/L_1 =\) 0.490. The degree of freedom left (\(W_1\) or \(L_1\)) can be determined by constraints either on the DC gain, the offset voltage or the flicker noise. In this example we will set a minimum DC gain. The latter is given by \[\begin{equation} A_{dc} =\frac{G_{m1}}{G_o} \end{equation}\] where \(G_o = G_{ds1b} + G_{ds2b}\) is the small-signal conductance to the AC ground at the output node. The output conductances are estimated with the following simple model \[\begin{equation} G_{dsi} = \frac{I_{Di}}{V_{Mi}} \end{equation}\] with \(V_{Mi} = \lambda_i \cdot L_i\). Note that this model of the output conductance is only a very rough approximation and the gain should therefore be checked by simulation. Some margin can be taken to ensure a sufficient DC gain.

A good trade-off for the output conductance is to split the output conductance \(G_o\) eually between M_1b and M_2b \(G_{ds1b}=G_{ds2b}=G_o/2\) or since M_1a-M_2b share the same bias current \(V_{M1b} = V_{M2b}\). The minimum length of M_1a-M_1b is then given by \(L_1 =\) 5.32 \(\mu m\), which gives a width \(W_1 =\) 2.60 \(\mu m\).

3.3.2 Sizing of M_3a-M_3b

The sizing of M_3a-M_3b is conditioned by the minimum common-mode input voltage \(V_{ic,min}\) to be handled according to \[\begin{equation} V_{ic,min} = V_{GS1} + V_{DSsat3}. \end{equation}\]

Because long-channel nMOS transistors have a small threshold voltage in this technology, the minimum common-mode input voltage \(V_{ic,min}\) can be low. If we choose an inversion coefficient for M_3a-M_3b equal to \(IC_3 =\) 20, we get \(V_{DSsat3} =\) 254 \(mV\) and \(V_{ic,min} =\) 733 \(mV\), which is low enough. We then get the specific current \(I_{spec3} =\) 14.300 \(\mu A\) and aspect ratio \(W_3/L_3 =\) 0.049. Since this \(W/L\) is rather small, we need to set \(W_3 = W_{min} =\) 200 \(nm\), and calculate the length \(L_3 =\) 4.09 \(\mu m\).

We can now size the current mirror M_2a-M_2b.

3.3.3 Sizing of M_2a-M_2b

The gate voltage of M_2a should be set as low as possible for a given maximum common mode input voltage still keeping M_1a in saturation. For a maximum input common-mode voltage \(V_{ic,max}\), the source-to-gate voltage of M_2a \(V_{SG2a}\) is given by \[\begin{equation} V_{SG2a} = V_{DD} - V_{icmax} + V_{GS1a} - V_{DSsat1a}. \end{equation}\]

The saturation voltage of M_1a-M_1b only depends on \(IC_1\). For the chosen \(IC_1 =\) 1.0 it is given by \(V_{DSsat1a} =\) 116 \(mV\).

The gate-to-source voltage \(V_{GS1a}\) is given by \[\begin{equation} V_{GS1a} = V_{T0n} + (n_{0n}-1)\,V_{S1} + n_{0n} \, U_T \, (v_p-v_s). \end{equation}\] In this design we have chosen to put M_1a-M_1b in a separate well, hence \(V_{SB1}=0\) and \(V_{GS1a}\) reduces to \[\begin{equation} V_{GS1a} = V_{T0n} + n_{0n} \, U_T \, (v_p-v_s), \end{equation}\] where \(v_p-v_s\) can be estimated from the inversion coefficient \(IC_1\). For the chosen \(IC_1 =\) 1.0, this gives \(V_{GS1} \cong\) 480 \(mV\). Setting the maximum input common-mode voltage to \(V_{ic,max} =\) 1.3 \(V\), results in \(V_{SG2} =\) 864 \(mV\), which corresponds to an inversion coefficient \(IC_2 =\) 34.1.

Because \(V_{SG2}\) also sets the quiescent output voltage, we could slightly increase \(V_{SG2}\) so that the quiescent output voltage is set at \(V_{DD}/2 =\) 0.9 \(V\). Choosing \(V_{SG2} =\) 900 \(mV\), corresponds to an inversion coefficient \(IC_2 =\) 40.1 and a saturation voltage \(V_{DSsat2} =\) 343 \(mV\). The specific current is then \(I_{spec2} =\) 8.74 \(nA\), the aspect ratio \(W_2/L_2 =\) 0.050 and the transconductance \(G_{m2} =\) 1.512 \(\mu A/V\),

The length of M_2a-M_2b is set by the dc gain similarly to the length of M_1a-M_1b resulting in \(L_2 =\) 5.32 \(\mu m\) from which we get its width \(W_2 =\) 270 \(nm\).

Since \(G_{m2}\) may become small and the gate area of M_2a-M_2b large, we need to check whether the non-dominant pole \(f_{p2}\) lies sufficiently high above the \(GBW\) to insure the desired phase margin. The non-dominant pole is given by \[\begin{equation} \omega_{p2} = \frac{G_{m2}}{C_2}, \end{equation}\] where \(C_2\) is given by \[\begin{equation} C_2 = 2(C_{GS2} + C_{GB2}) \end{equation}\] Assuming M₂ is in saturation, we have \[\begin{equation} C_{GS2} \cong W_2\,L_2\,C_{ox} \cdot c_{gsi} + C_{GSop} \cdot W_2 \end{equation}\] where \(c_{gsi}\) is the normalized intrinsic gate-to-source capacitance which is typically equal to \(2/3\) in strong inversion and is proportionnal to \(IC\) in weak inversion. The gate-to-bulk capacitance \(C_{GB2}\) is given by \[\begin{equation} C_{GB2} \cong \,W_2\,L_2\,C_{ox} \cdot c_{gbi} + C_{GBop} \cdot W_2, \end{equation}\] where \(c_{gbi}\) is the normalized gate-to-bulk intrinsic capacitance given by \[\begin{equation} c_{gbi} = \frac{n-1}{n} \cdot c_{gsi}. \end{equation}\]

The capacitance at node 2 scales with \(W_2\) and \(L_2\) according to \[\begin{equation} C_2 = C_{WL} \cdot W_2\,L_2 + C_W \cdot W_2, \end{equation}\] with \[\begin{align} C_{WL} &= 2\,C_{ox} \cdot (c_{gsi} + c_{gbi}),\\ C_W &= 2(C_{GSop} + G_{GBop}). \end{align}\]

For the \(W_2\) and \(L_2\) chosen above, this results in \(C_{GS2} =\) 7.50 \(fF\), \(C_{GB2} =\) 1.11 \(fF\), \(C_2 =\) 17.21 \(fF\) and finally \(f_{p2} =\) 13.988 \(MHz\), which is to close to the specified \(GBW\).

We therefore need to reduce \(IC_2\) which will increase the \(G_m/I_D\) and since the current is set by the bias current \(I_b\), it will increase \(G_{m2}\). If \(W_2\) is set to its minimum value \(W_{min}\), decreasing \(IC_2\) keeping the same current, will increase the \(W_2/L_2\). With \(W_2\) set, this leads to a decrease of \(L_2\) and hence a decrease of \(C_2\). The increase of \(G_{m2}\) and decrease of \(C_2\) leads to an increase of \(f_{p2}\), as required. We can use the following script to find the required \(IC\) for having the non-dominant pole at 10 times the \(GBW\).

Running the optimizer results in an inversion coefficient \(IC_2 =\) 14.7, a transconductance \(G_{m2} =\) 2.375 \(\mu A/V\), a transconductance ratio \(G_{m1}/G_{m2} =\) 2.769, an aspect ratio \(W_2/L_2 =\) 0.138 and finally a width and length \(W_2 =\) 200 \(nm\) and \(L_2 =\) 1.45 \(\mu m\). As expected, the non-domiant pole is \(f_{p2} =\) 100 \(MHz\) corresponding to the target ratio \(f_{p2}/GBW =\) 10.

Figure 9: Length \(L_2\) and width \(W_2\) of M_2a-M_2b versus \(IC_2\) for a given \(f_{{p2}}/GBW\) ratio.

We see that \(IC_2\) has been increased, increasing \(G_{m2}\) and \(W_2/L_2\) for the given current \(I_b\). Since \(W_2\) hits \(W_{min}\), the length \(L_2\) has been slightly increased, increasing \(C_2\) at the same time to set \(f_{p2}\) at 10 times the GBW. Now, this has also increased \(V_{SG2}\)

\(V_{SG2} =\) 713 \(mV\),

which reduces the maximum input common-mode voltage to

\(V_{ic,max} =\) 1.451 \(V\).

The sizing process is now finished. The resulting design is summarized in the next section.

3.4 Summary

3.4.1 Specifications

The specifications are recalled in Table 5.

Table 5: OTA specifications.

Specification	Symbol	Value	Unit
Minimum DC gain	\(A_{{dc}}\)	60	\(dB\)
Minimum gain-bandwidth product	\(GBW\)	10	\(MHz\)
Load capacitance	\(C_L\)	0.1	\(pF\)
Maximum input-referred random offset voltage	\(V_{{os,max}}\)	4	\(mV\)
Phase margin	\(PM\)	60	\(^{\circ}\)

3.4.2 Bias

The bias information are summarized in Table 6.

Table 6: OTA bias.

Bias voltage or current	Symbol	Value	Unit
Supply voltage	\(V_{{DD}}\)	1.8	\(V\)
Bias current	\(I_b\)	350	\(nA\)

3.4.3 Transistor information

The transistor sizes and large-signal variables are summarized in Table 7, whereas Table 8 gives the small-signal and thermal noise parameters. An Excel table is generated with more information (e.g. all the parasitic capacitances).

Table 7: Transistor size and bias information.

Transistor	\(W\;[\mu m]\)	\(L\;[\mu m]\)	\(I_D\;[nA]\)	\(I_{{spec}}\;[nA]\)	\(IC\)	\(V_G-V_{{T0}}\;[mV]\)	\(V_{{DSsat}}\;[mV]\)
M1a	2.60	5.32	350	349	1.0	15	116
M1b	2.60	5.32	350	349	1.0	15	116
M2a	0.20	1.45	350	24	14.7	157	224
M2b	0.20	1.45	350	24	14.7	157	224
M3a	0.20	4.09	700	35	20.0	191	254
M3b	0.20	4.09	700	35	20.0	191	254

Table 8: Transistor small-signal and thermal noise parameters.

Transistor	\(G_{{spec}}\;[\mu A/V]\)	\(G_{{ms}}\;[\mu A/V]\)	\(G_m\;[\mu A/V]\)	\(G_{{ds}}\;[nA/V]\)	\(\gamma_n\)
M1a	13.505	8.356	6.573	3.289	0.717
M1b	13.505	8.356	6.573	3.289	0.717
M2a	0.923	3.101	2.375	12.066	0.821
M2b	0.923	3.101	2.375	12.066	0.821
M3a	1.351	5.408	4.254	8.557	0.805
M3b	1.351	5.408	4.254	8.557	0.805

4 OTA Characteristics

In this section, we check whether the specs are achieved.

4.1 Open-loop gain

The calculated OTA features are given in Table 9.

Table 9: OTA gain variables.

Symbol	Theoretical Value	Unit
\(A_{dc}\)	53	\(dB\)
\(G_{m1}\)	6.573	\(\mu A/V\)
\(G_{m2}\)	2.375	\(\mu A/V\)
\(f_0\)	24.438	\(kHz\)
\(GBW\)	10.461	\(MHz\)
\(f_{p2}\)	110.282	\(MHz\)
\(f_{z2}\)	220.563	\(MHz\)

Warning

The slight differences between the value of \(f_{p2}\) calculated during the design process and the value shown in Table 9 is due to the width and length rounding process.

Using the values given in Table 9, we can now plot the gain response shown in Figure 10.

Figure 10: OTA theoretical transfer function.

4.2 Input-referred noise

We can now compute all the parameters needed for the calculation of the OTA thermal noise excess factor and its input-referred thermal noise resistance. They are given in Table 10.

Table 10: OTA thermal noise parameters.

Symbol	Theoretical Value	Unit
\(G_{m1}\)	6.573	\(\mu A/V\)
\(G_{m2}\)	2.375	\(\mu A/V\)
\(G_{m1}/G_{m2}\)	2.768	-
\(\gamma_{n1}\)	0.717	-
\(\gamma_{n2}\)	0.821	-
\(\eta_{th}\)	0.414	-
\(R_{nt}\)	308.316	\(k \Omega\)
\(\gamma_{ota}\)	2.026	-
\(\sqrt{S_{ninth}}\)	71.454	\(nV/\sqrt{Hz}\)
\(10 \cdot \log(S_{ninth})\)	-142.919	\(dBv/\sqrt{Hz}\)

From Table 10, we see that \(\eta_{th} =\) 0.414 and hence that the OTA thermal noise excess factor is only slightly larger than that of the differential pair. This is due to the \(G_{m1}/G_{m2}\) ratio as shown in Table 10.

We can now compute all the parameters needed for the calculation of the input-referred flicker noise and the corner frequency. They are given in Table 11.

Table 11: OTA flicker noise parameters.

Symbol	Theoretical Value	Unit
\((G_{m1}/G_{m2})^2\)	7.7	-
\(\rho_p/\rho_n\)	8.3	-
\(\frac{{W_1 \cdot L_1}}{{W_2 \cdot L_2}}\)	47.7	-
\(\eta_{fl}\)	42.997	-
\(\sqrt{{S_{{ninfl}}(1\,Hz)}}\)	78.1	\(\mu V/\sqrt{{Hz}}\)
\(10 \cdot \log(S_{{ninfl}}(1\,Hz))\)	-82.1	\(dBv/\sqrt{{Hz}}\)
\(f_k\)	1195	\(kHz\)

From Table 11, we see that M_2a-M_2b contribute 42.997 times more than M_1a-M_1b. This is coming from the fact that \(W_1\,L_1\) is 48 times larger than \(W_2\,L_2\) and that \(\rho_p\) is 8.3 times larger than \(\rho_n\). The flicker noise will therefore be dominated by M_2a-M_2b.

We can plot the input-reffered noise which is shown in Figure 11.

Figure 11: OTA theoretical input-referred noise PSD.

4.3 Input-referred offset

The variance of the input-referred offset is given by \(\eqref{eqn:sigma_vos}\) which is repeated below \[\begin{equation} \sigma_{Vos}^2 = \sigma_{VT}^2 + \sigma_{\beta}^2, \end{equation}\] where \(\sigma_{VT}\) is the \(V_T\)-mismatch given by \[\begin{equation} \sigma_{VT}^2 = \sigma_{V_{T1}}^2 \cdot (1 + \xi_{V_T}). \end{equation}\] where \(\xi_{V_T}\) represents the \(V_T\)-mismatch contribution to the input-referred offset of the current mirror relative to that of the differential pair \[\begin{equation} \xi_{V_T} = \left(\frac{G_{m2}}{G_{m1}}\right)^2 \cdot \frac{\sigma_{V_{T2}}^2}{\sigma_{V_{T1}}^2} = \left(\frac{G_{m2}}{G_{m1}}\right)^2 \cdot \left(\frac{A_{V_{Tp}}}{A_{V_{Tp}}}\right)^2 \cdot \frac{W_1\,L_1}{W_2\,L_2}. \end{equation}\] \(\sigma_{\beta}\) is the \(\beta\)-mismatch given by \[\begin{equation} \sigma_{\beta}^2 = \left(\frac{I_b}{G_{m1}}\right)^2 \cdot \sigma_{\beta_1}^2 \cdot (1 + \xi_{\beta}), \end{equation}\] where \(\xi_{\beta}\) represents the \(\beta\)-mismatch contributions to the input-referred offset of the current mirror relative to that of the differential pair \[\begin{equation} \xi_{\beta} = \frac{\sigma_{\beta_2}^2}{\sigma_{\beta_2}^2} = \left(\frac{A_{\beta_p}}{A_{\beta_n}}\right)^2 \cdot \frac{W_1\,L_1}{W_2\,L_2}, \end{equation}\] where \[\begin{align} \sigma_{\beta_i}^2 &= \frac{A_{\beta}^2}{W_i L_i} \qquad i=1,2,\\ \sigma_{V_{T0i}}^2 &= \frac{A_{VT}^2}{W_i L_i} \qquad i=1,2. \end{align}\]

The parameter for calculating the standard deviation of the input-referred offset voltage are given in Table 12.

Table 12: OTA input-referred offset parameters.

Symbol	Theoretical Value	Unit
\(\sigma_{{VT1}}\)	1.3444	\(mV\)
\(\sigma_{{VT2}}\)	9.28344	\(mV\)
\(\sigma_{{\beta1}}\)	0.268879	\(\%\)
\(\sigma_{{\beta2}}\)	1.85669	\(\%\)
\(\xi_{{VT}}\)	6.22439	-
\(\xi_{{\beta}}\)	47.6829	-
\(\sigma_{{V_T}}^2\)	13.0574	\(mV^2\)
\(\sigma_{{V_T}}\)	3.6135	\(mV\)
\(\sigma_{{\beta}}^2\)	0.998046	\(mV^2\)
\(\sigma_{{\beta}}\)	0.999022	\(mV\)
\(\sigma_{{Vos}}\)	3.749	\(mV\)

From Table 12, we see that the dominant contribution to the input-referred offset voltage is due to the differential pair M_1a-M_1b. The resulting total input-referred offset voltage is \(\sigma_{Vos} =\) 3.749 \(mV\).

4.4 Current and power consumption

The total current consumption without accounting for the bias string M_3a is simply \(I_{tot} = 2\,I_b =\) 700 \(nA\), resulting in power consumption \(P=V_{DD} \cdot I_{tot} =\) 1.3 \(\mu W\).

5 Simulation results from ngspice

The theoretical results can be validated by comparing them to the results obtained from simulations performed with ngspice. The cells below will run the simulations with ngspice. In order to run the simulations you need to have ngspice installed. Please refer to the ngspice instructions.

Note

The simulations are performed with ngspice [4] using the EKV 2.6 compact model [5] [12] [1]. For ngspice, we use the original Verilog-A implementation of EKV 2.6 [7] modified by C. Enz to get the operating point informations and available on the Gitub va-models site provided by D. Warning at [6] [13]. The Verilog-A code was then compiled with OpenVAF [14] to generate the OSDI for running it with ngspice. The parameters correspond to a generic 180 nm bulk CMOS process [8].

5.1 Operating point

We first write the parameter file for this specific design for running the ngspice simulations. Before running the AC and NOISE simulations, we first need to check the quiescent voltages and currents and the operating points of all transistors by running an .OP simulation. The node voltages are extracted from the .ic file and presented in Table 13.

Table 13: OTA node voltages with the OTA in open-loop without offset correction.

Node	Voltage
vdd	1.8
inp	0.9
inn	0.9
id	0
ic	0.9
out	1.087
1	0.419764
2	1.087
3	0.752329

From Table 13, we see that the ouput voltage \(V_{outq} =\) 1087 \(mV\) of the open-loop circuit is close to the input common mode voltage \(V_{ic} =V_{DD}/2 =\) 900 \(mV\). Since the operating point is in the high gain region, we don’t need to impose an offset voltage to bring the output voltage in the high gain region.

The operating point information for all transistors coming from the EKV2.6 compact model are extracted from the ngspice .op.dat file. The data is split into the large-signal operating informations presented in Table 14, the small-signal operating point informations shown in Table 15 and the noise operating point informations in Table 16.

Table 14: Large-signal operating point information extracted from ngspice .op file for each transistor.

Transistor	\(I_D\;[nA]\)	\(I_{spec}\;[nA]\)	\(IC\) [-]	\(n\) [-]	\(V_{DSsat}\;[mV]\)
M1a	349.0	351.6	0.993	1.27	155
M1b	349.0	351.6	0.993	1.27	155
M2a	349.0	28.4	12.406	1.31	286
M2b	349.0	28.4	12.406	1.31	286
M3a	700.0	37.6	18.681	1.27	327
M3b	697.9	37.5	18.669	1.27	327

Table 15: Small-signal operating point information extracted from ngspice .op file for each transistor.

Transistor	\(G_m\;[\mu A/V]\)	\(G_{ms}\;[\mu A/V]\)	\(G_{ds}\;[nA/V]\)
M1a	6.455	8.313	2.566
M1b	6.455	8.313	2.566
M2a	2.456	3.308	5.544
M2b	2.456	3.308	5.544
M3a	4.222	5.441	4.881
M3b	4.208	5.427	8.822

Table 16: Noise operating point information extracted from ngspice .op file for each transistor.

Transistor	\(R_n\;[k\Omega]\)	\(\sqrt{S_{ID,th}}\;[nA/\sqrt{Hz}\)	\(\gamma_n\) [-]	\(\sqrt{S_{ID,fl}}\) at 1Hz \([nA/\sqrt{Hz}]\)
M1a	114.185	43.506	0.737	8317.76
M1b	114.185	43.506	0.737	8317.76
M2a	350.763	76.251	0.861	150982
M2b	350.763	76.251	0.861	150982
M3a	200.120	57.595	0.845	31591.5
M3b	200.936	57.712	0.846	31591.5

We can check the bias voltages and operating region of each transistor which are given in Table 17.

Table 17: Bias voltages and operating regions of each transistor.

Trans.	Type	Funct.	\(V_G\;[V]\)	\(V_S\;[V]\)	\(V_D\;[V]\)	\(V_{DS}\;[mV]\)	\(V_{DSsat}\;[mV]\)	Reg.	Sat.
M1a	n	DP	0.480	0.000	0.667	667	155	MI	sat
M1b	n	DP	0.480	0.000	0.667	667	155	MI	sat
M2a	p	CM	0.713	0.000	0.713	713	286	SI	sat
M2b	p	CM	0.713	0.000	0.713	713	286	SI	sat
M3a	n	CM	0.752	0.000	0.752	752	327	SI	sat
M3b	n	CM	0.752	0.000	0.420	420	327	SI	sat

We see that all transistors are biased in saturation. The operating points looks fine. We can now proceed with the large-signal DC simulation.

5.2 Large-signal differential transfer characteristic

We now simulate the large-signal DC input-output transfer characteristic. The simulation result is presented in Figure 12.

Figure 12: Simulated large-signal input-output characteristic.

From Figure 12, we see that the output swing is about \(V_{out,swing} \cong\) 700 \(mV\) which is rather small. We can now zoom into the high gain region and estimate the offset voltage and the output swing. The simulation results are presented in Figure 13.

Figure 13: Zoom of the simulated large-signal input-output characteristic in the gain region.

We see that the required offset voltage to bring the output voltage to \(V_{outq} =\) 900 \(mV\) is equal to \(V_{os} =\) -232.963 \(\mu V\), which is small.

5.3 Open-loop gain

After having checked the operating point information and making sure that the OTA output is not saturated and in the high gain region, we can now perform the AC simulation. The simulation results are compared to the theoretical estimations in Figure 14.

Figure 14: Simulated gain response compared to theoretical estimation.

We see an almost perfect match between the small-signal simulations and the theoretical results except at higher frequency where additional poles due to parasitic capacitances that have not been accounted for introduce additional phase shift. We now will peform the noise simulations.

5.4 Input-referred noise

We can compare the theoretical input-referred noise to that obtained from simulations. The simulation results are presented in Figure 15.

Figure 15: Simulated input-referred noise PSD compared to theoretical estimation.

From Figure 15, we see a good match between the simulated and theoretical input-referred noise PSD. The contributions of M_1a-M_1b and M_2a-M_2b to the input-referred white noise PSD are detailed in Figure 16 and compared to the theoretical white noise.

Figure 16: Breakdown of the contributions to the simulated input-referred white noise PSD.

We can observe that the total simulated white noise is about 0.306 dB higher than the theoretical estimation, which is acceptable. The white noise is dominated by the differential pair M_1a-M_1b which is \(1+\eta_{th} =\) 1.445 times (or 1.599 dB) lower than the total white noise. The contribution of M_2a-M_2b is about \(\eta_{th} =\) 0.445 times (or 3.516 dB) lower than the contribution of M_1a-M_1b. The simulated value of \(\eta_{th} =\) 0.445 is about 1.075 larger than the theoretical estimation. This results in an OTA thermal noise excess factor \(\gamma_{n,ota} =\) 2.135 that is slightly larger than the predicted value \(\gamma_{n,ota} =\) 2.026.

Figure 17 presents the breakdown of the contributions of M_1a-M_1b and M_2a-M_2b to the input-referred flicker noise. Contrary to the white noise, the flicker noise is largely dominated by the contribution of the current mirror M_2a-M_2b which was already observed in the OTA characteristic section. It is due to the fact that \(W_1\,L_1\) is 48 times larger than \(W_2\,L_2\) and that \(\rho_p\) is 8.3 times larger than \(\rho_n\).

The breakdown of the contributions of M_1a-M_1b and M_2a-M_2b to the total input-referred noise is summarized in Figure 17. We can observe that the simulation is close to the theoretical estimation.

Figure 17: Breakdown of the contributions to the simulated input-referred flicker noise PSD.

Figure 18: Breakdown of the contributions to the simulated input-referred noise PSD.

5.5 Input common-mode voltage range

We can check the input common-mode voltage range by connecting the OTA as a voltage follower and sweeping the positive input. The result is shown in Figure 19.

Figure 19: Simulated input common-mode voltage range.

As shown in Figure 19, the output follows the input voltage up to 1.4 \(V\). So the input common-mode voltage range is about 1.4 \(V\).

5.6 Step-response

Figure 20: Schematic of the OTA connected as a voltage follower.

In this section we will check the step response of the OTA operating as a voltage follower as shown in Figure 20 with its output connected to the negative input and with the same load capacitance \(C_L =\) 0.1 \(pF\). According to the input common-mode voltage range established above, we will set the input common-mode voltage to \(V_{ic} =\) 0.9 \(V\) to leave enough room for the large step.

5.6.1 Small-step

We start by imposing a small step \(\Delta V_{in} =\) 10 \(mV\) on top of a common mode voltage \(V_{ic} =\) 0.9 \(V\). The simulation results are shown in Figure 21 where \(\Delta V_{in}(t) \triangleq V_{in+}(t) - V_{ic}\) and \(\Delta V_{out}(t) \triangleq V_{out}(t) - V_{outq}\) with \(V_{outq}\) the quiescent output voltage at the operating point before the step is applied. \(\Delta V_{in}\) and \(\Delta V_{out}\) are compared to the response of a single pole circuit having a cut-off frequency equal to the \(GBW\). We can observe a very good match between the simulated and theoretical small step response.

Figure 21: Step response of the OTA as a voltage follower for a small input step.

5.6.2 Large step

We now impose a larger step \(\Delta V_{in} =\) 300 \(mV\) on top of a common mode voltage \(V_{ic} =\) 300 \(mV\). The simulation results are shown in Figure 22 where \(\Delta V_{in}(t) \triangleq V_{in+}(t) - V_{ic}\) and \(\Delta V_{out}(t) \triangleq V_{out}(t) - V_{outq}\) with \(V_{outq}\) the quiescent output voltage at the operating point before the step is applied. \(\Delta V_{in}\) and \(\Delta V_{out}\) are compared to the response of a single pole circuit having a cut-off frequency equal to the \(GBW\). We now observe the effect of slew-rate which increases the settling time.

Figure 22: Step response of the OTA as a voltage follower for a large input step highlighting the slew-rate effect.

5.7 Current and power consumption

The total current consumption without accounting for the bias string M_3a is simply \(I_{tot} = 2\,I_b =\) 700 \(nA\), resulting in power consumption \(P=V_{DD} \cdot I_{tot} =\) 1.3 \(\mu W\).

6 Conclusion

This notebook presented the analysis, design and verification of the simple 5 transistors OTA. The detailed analysis provided all the equations that were then used in the design phase to reach the target specifications. The design was then performed using the inversion coefficient approach with the sEKV transistor model for a generic 180 nm bulk CMOS process. The theoretical performance resulting from the design were then evaluated. The design was then verified by simulation with ngspice [4] using the EKV 2.6 compact model [5] [12] [1] and the parameters of a generic 180 nm bulk CMOS process. After carefully checking the operating point, the large-signal transfer characteristic was simulated. Then the small-signal open-loop transfer function was simulated. The target gain-bandwidth \(GBW\) and DC gain gain are achieved. The input-referred noise was then simulated and compared to the theoretical estimation. It was shown that the flicker noise is dominated by the pMOS current mirror, while the white noise is dominated by the differential pair. The input common-mode voltage range was then simulated with the OTA connected as a voltage follower. The input voltage is limited to 1.4 \(V\). Finally, the small-signal step response was simulated and successfully compared to the theoretical small step response. The step-response with a large input step highlighted the effect of slew-rate resulting in an increased settling time.

7 References

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