Fundamentals of Analog VLSI Design
Exercise 2 - Solution
Differential pair - Inverter - Velocity saturation
1 Problem 1: The differential pair
1.1 Both transistors in weak inversion
1.1.1 Large-signal characteristic
In the following analysis, we will assume that \(M_1\) and \(M_2\) are perfectly matched, leading to \[\begin{align} V_{T01} &= V_{T02} = V_{T0},\\ I_{D01} &= I_{D02} = I_{D0},\\ n_1 &= n_2 =n. \end{align}\] In the case both transistors are biased in weak inversion and saturation and since the bulks of \(M_1\) and \(M_2\) are connected to the ground, the drain currents are then given by \[\begin{align} I_1 &= I_{D0} \cdot e^{\frac{V_{i1}-n\,V_S}{n U_T}},\\ I_2 &= I_{D0} \cdot e^{\frac{V_{i2}-n\,V_S}{n U_T}}. \end{align}\] The differential output current is then given by \[\begin{equation}\label{eqn:iod1} I_{od} \triangleq I_1-I_2 = I_{D0} \cdot e^{-\frac{V_S}{U_T}} \cdot \left[e^{\frac{V_{i1}}{n U_T}}-e^{\frac{V_{i2}}{n U_T}}\right]. \end{equation}\] Now, the sum of \(I_1\) and \(I_2\) is set by the bottom current source \[\begin{equation} I_1+I_2 = 2 I_b, \end{equation}\] leading to \[\begin{equation} 2 I_b = I_{D0} \cdot e^{-\frac{V_S}{U_T}} \cdot \left[e^{\frac{V_{i1}}{n U_T}}+e^{\frac{V_{i2}}{n U_T}}\right] \end{equation}\] from which we get \[\begin{equation}\label{eqn:exp_vs} I_{D0} \cdot e^{-\frac{V_S}{U_T}} = \frac{2 I_b}{e^{\frac{V_{i1}}{n U_T}}+e^{\frac{V_{i2}}{n U_T}}} \end{equation}\] Replacing \(\eqref{eqn:exp_vs}\) in \(\eqref{eqn:iod1}\) results in \[\begin{equation}\label{eqn:iod2} I_{od} = 2 I_b \cdot \frac{e^{\frac{V_{i1}}{n U_T}}-e^{\frac{V_{i2}}{n U_T}}} {e^{\frac{V_{i1}}{n U_T}}+e^{\frac{V_{i2}}{n U_T}}}. \end{equation}\] The input voltages can be written in terms of the differential and common mode voltages according to \[\begin{align} V_{i1} &= V_{ic} + \frac{V_{id}}{2},\\ V_{i2} &= V_{ic} - \frac{V_{id}}{2}. \end{align}\] Replacing in \(\eqref{eqn:iod2}\) results in \[\begin{equation}\label{eqn:iod3} I_{od} = 2 I_b \cdot \frac{e^{\frac{V_{id}}{2 n U_T}}-e^{-\frac{V_{id}}{2 n U_T}}} {e^{\frac{V_{id}}{2 n U_T}}+e^{-\frac{V_{id}}{2 n U_T}}} = 2 I_b \cdot \tanh\left(\frac{V_{id}}{2 n U_T}\right). \end{equation}\] The differential output current \(I_{od}\) normalized to \(2 I_b\) can then be written as \[\begin{equation} i_{od} \triangleq \frac{I_{od}}{2 I_b} = \tanh(v_{id}), \end{equation}\] where \(v_{id} \triangleq V_{id}/(2n U_T)\).
1.1.2 Small-signal characteristic
The small-signal transconductance is defined by \[\begin{equation} G_m \triangleq \frac{d I_{od}}{d V_{id}} = G_{m0} \cdot \left[1 - \tanh^2\left(\frac{V_{id}}{2 n U_T}\right)\right] \end{equation}\] where \(G_{m0}\) is the transconductance for \(V_{id}=0\) \[\begin{equation} G_{m0} = \frac{I_b}{n U_T}. \end{equation}\] The maximum transconductance \(G_{m0}\) of the differential pair therefore corresponds to the transconductance of a single transistor for \(V_{id}=0\) (i.e. when \(I_1=I_2=I_b\)).
The small-signal transconductance normalized to \(G_{m0}\) is then given by \[\begin{equation} g_m \triangleq \frac{G_m}{G_{m0}} = 1-\tanh^2\left(v_{id}\right). \end{equation}\]
The normalized differential output current \(i_{od}\) and normalized transconductance \(g_m\) are plotted below versus the normalized differential input voltage \(v_{id}\)
From Figure 2, we see that the large-signal nonlinear characteristic can be approximated by a piecewise linear characteristic where the middle part has the slope of the nonlinear characteristic at \(v_{id}=0\). The linear range can then be defined as the input voltage covered by the middle linear characteristic. In weak inversion the linear range is about \(4 n U_T\) which is about 135 mV at room temperature for \(n=1.3\). This is rather small.
1.2 Both transistors in strong inversion
1.2.1 Large-signal characteristic
We again will assume that the two transistors are perfectly matched, which means that \[\begin{align} V_{T01} &= V_{T02} = V_{T0},\\ \beta_1 &= \beta_2 = \beta,\\ n_1 &= n_2 =n. \end{align}\] In the case both transistors are biased in strong inversion and saturation and since the bulks of \(M_1\) and \(M_2\) are connected to the ground, the drain currents are given by \[\begin{align} I_1 &= \frac{\beta}{2 n} \cdot (V_{i1}-V_{T0}-n\,V_S)^2,\\ I_2 &= \frac{\beta}{2 n} \cdot (V_{i2}-V_{T0}-n\,V_S)^2, \end{align}\] where \(V_S\) is the voltage of the common source node. Solving the above equations together with \[\begin{align} I_{od} &= I_1-I_2,\\ I_1+I_2 &= 2 I_b,\\ V_{i1} &= V_{ic}+\frac{V_{id}}{2},\\ V_{i2} &= V_{ic}-\frac{V_{id}}{2},\\ V_{id} &= V_{i1}-V_{i2}, \end{align}\] leads to \[\begin{equation} I_{od} = V_{id} \cdot \sqrt{\frac{\beta}{2 n I_b}} \cdot \sqrt{1-\frac{\beta}{2 n I_b} \cdot \left(\frac{V_{id}}{2}\right)^2} \end{equation}\] valid for \[\begin{equation} |V_{id}| < 2 \sqrt{\frac{2 n I_b}{\beta}} = 2 (V_{ic}-V_{T0}-V_S). \end{equation}\] The differential output current \(I_{od}\) can be normalized to the maximum output current \(2 I_b\) \[\begin{equation} i_{od} \triangleq \frac{I_{od}}{2 I_b} = v_{id} \cdot \sqrt{1 - \left(\frac{v_{id}}{2}\right)^2}, \end{equation}\] valid for \[\begin{equation} |v_{id}| < \sqrt{2}, \end{equation}\] where \[\begin{equation} v_{id} \triangleq \frac{V_{id}}{\sqrt{2 n I_b/\beta}} = \frac{V_{id}}{V_G-V_{T0}- n\,V_S}. \end{equation}\]
1.2.2 Small-signal transconductance
The small-signal transconductance is defined as \[\begin{equation} G_m \triangleq \frac{d I_{od}}{d V_{id}}, \end{equation}\] which is given by \[\begin{equation} G_m = G_{m0} \cdot \frac{2-v_{id}^2}{\sqrt{4-v_{id}^2}}, \end{equation}\] where \[\begin{equation} G_{m0} = \sqrt{\frac{2 \beta I_b}{n}} \end{equation}\] is the transconductance for \(V_{id}=0\) which also corresponds to the transconductance of M1 or M2 for \(V_{id}=0\).
The large-signal normalized differential output current and the normalized transconductance are plotted versus \(v_{id}\) in Figure 3.
Similarly to what has been done in weak inversion we can approximate the nonlinear characteristic by a piecewise linear model as shown in Figure 3. The linear range is now proportionnal to the overdrive voltage according to \(2(V_G-V_{T0}-n\,V_S)\), which is much larger than what we get in weak inversion. We can therefore make the differential pair more linear by increasing the overdrive voltage. However, this comes at the cost of a reduced current efficiency \(G_m/I_b\).
1.3 Optional: Both transistors in any modes of operation (saturation)
1.3.1 Large-signal characteristic
We can use the EKV charge-based model to express the gate voltages of \(M_1\) and \(M_2\) in terms of \(q_{s1}\) and \(q_{s2}\) according to \[\begin{align} \frac{V_{i1}-V_{T0}-n\,V_S}{n\,U_T} &= 2 q_{s1} + \ln(q_{s1}),\\ \frac{V_{i2}-V_{T0}-n\,V_S}{n\,U_T} &= 2 q_{s2} + \ln(q_{s2}). \end{align}\] If we want to be consistent with the analysis of the differential pair in weak inversion we need to use the same normalization. This means that the voltages need to be normalized to \(2 n\,U_T\), leading to \[\begin{align} v_{i1}-v_{t0n}-v_s &= q_{s1} + \tfrac{1}{2}\,\ln(q_{s1}),\label{eqn:vi1_vt0_vs}\\ v_{i2}-v_{t0n}-v_s &= q_{s2} + \tfrac{1}{2}\,\ln(q_{s2}),\label{eqn:vi2_vt0_vs} \end{align}\] where \[\begin{align} v_{i1} &\triangleq \frac{V_{i1}}{2 n U_T},\\ v_{i2} &\triangleq \frac{V_{i2}}{2 n U_T},\\ v_s &\triangleq \frac{V_S}{2 n U_T}. \end{align}\] The normalized differential input voltage \(v_{id}\) is then given by subtracting \(\eqref{eqn:vi2_vt0_vs}\) to \(\eqref{eqn:vi1_vt0_vs}\) resulting in \[\begin{equation}\label{eqn:vid_qs1_qs2} v_{id} \triangleq \frac{V_{id}}{2 n\,U_T} = v_{i1}-v_{i2} = q_{s1}-q_{s2}+\tfrac{1}{2}\,\ln\left(\frac{q_{s1}}{q_{s2}}\right) \end{equation}\]
We need to be careful with the normalization of the currents. In order to have the output differential current \(I_{od}=I_1-I_2\) normalized to the maximum output current \(2 I_b\), like it was done for the analysis in weak and strong inversion, we need to define the normalized currents \(i_1\), \(i_2\) and \(i_{od}\) as \[\begin{align} i_1 &\triangleq \frac{I_1}{2 I_b},\\ i_2 &\triangleq \frac{I_2}{2 I_b},\\ i_{od} &\triangleq \frac{I_{od}}{2 I_b} = \frac{I_1-I_2}{2 I_b} = i_1-i_2. \end{align}\] The normalized source charges \(q_{s1}\) and \(q_{s2}\) are related to the normalized drain currents \(i_{d1}\) and \(i_{d2}\) according to \[\begin{align} i_{d1} &\triangleq \frac{I_1}{I_{spec}} = q_{s1} \cdot (q_{s1}+1),\\ i_{d2} &\triangleq \frac{I_2}{I_{spec}} = q_{s2} \cdot (q_{s2}+1). \end{align}\] Notice that \(i_1\) and \(i_2\) are different than \(i_{d1}\) and \(i_{d2}\) since the former are normalized to \(2 I_b\), whereas the latter are normalized to \(I_{spec}\). They are related according to \[\begin{align} i_1 &= \frac{i_{d1}}{2 IC_q},\\ i_2 &= \frac{i_{d2}}{2 IC_q}, \end{align}\] where \[\begin{equation} IC_q \triangleq \frac{I_b}{I_{spec}} \end{equation}\] corresponds to the inversion coefficient of \(M_1\) and \(M_2\) at the quiescent operating point, i.e. for \(V_{id}=0\).
Solving the above set of equations for \(q_{s1}\) and \(q_{s2}\) results in \[\begin{align} q_{s1} &= \frac{\sqrt{4 IC_q\,(1+i_{od})+1}-1}{2},\label{eqn:qs1_iod}\\ q_{s2} &= \frac{\sqrt{4 IC_q\,(1-i_{od})+1}-1}{2}.\label{eqn:qs2_iod} \end{align}\] We can now sweep the normalized differential output current for a given \(IC_q\) and then calculate \(q_{s1}\) and \(q_{s2}\) according to \(\eqref{eqn:qs1_iod}\) and \(\eqref{eqn:qs2_iod}\) and use them to calculate \(v_{id}\) according to \(\eqref{eqn:vid_qs1_qs2}\). The result is plotted in Figure 4 for different \(IC_q\).
We clearly see that increasing the inversion coefficient \(IC_q\) from weak inversion to strong inversion extends the linear range from \(4 n U_T\) to \(2(V_{ic}-V_{T0}-nV_S)\), where \(V_{ic} \triangleq (V_{i1}+V_{i2})/2\) is the input common-mode voltage. However this comes at the cost of a reduced transconductance efficiency \(G_{m0}/I_b\).
1.3.2 Small-signal transconductance
In the previous section we have derived an expression of \(V_{id}\) in terms of \(q_{s1}\) and \(q_{s2}\) which depend on \(I_{od}\). We can derive the transconductance by differentiating \(V_{id}\) wrt \(I_{od}\) \[\begin{equation} \frac{dV_{id}}{dI_{od}} = \frac{1}{G_m} \end{equation}\] or in normalized form \[\begin{equation} \frac{dv_{id}}{di_{od}} \cdot \frac{2 n\,U_T}{2 I_b} = \frac{1}{G_m}. \end{equation}\] The transconductance can then be written as \[\begin{equation} G_m \cdot \frac{n\,U_T}{I_b} = \left(\frac{dv_{id}}{di_{od}}\right)^{-1} = \frac{di_{od}}{dv_{id}} = g_m. \end{equation}\] so that \[\begin{equation} g_m \triangleq \frac{di_{od}}{dv_{id}} = \frac{G_m}{I_b/(n\,U_T)}. \end{equation}\] It can be shown that \[\begin{equation} g_m = \frac{4}{IC_q} \cdot \frac{q_{s1} \cdot q_{s2}}{q_{s1}+q_{s2}} \end{equation}\] with \(q_{s1}\) and \(q_{s2}\) given by \(\eqref{eqn:qs1_iod}\) and \(\eqref{eqn:qs2_iod}\).
Now, we want to plot \(g_m\) normalized to its value at \(v_{id}=0\) \[\begin{equation} g_{m0} \triangleq g_m(v_{id}=0). \end{equation}\] For \(v_{id}=0\), we have \(i_{od}=0\) and from \(\eqref{eqn:qs1_iod}\) and \(\eqref{eqn:qs2_iod}\), we get \[\begin{equation}\label{eqn:qs_ICq} q_s \triangleq = \left.q_{s1}\right|_{v_{id}=0} = \left.q_{s2}\right|_{v_{id}=0} = \frac{\sqrt{4 IC_q+1}-1}{2}. \end{equation}\] \(g_{m0}\) can therefore be written as \[\begin{equation} g_{m0} = \frac{q_s}{IC_q} = \frac{\sqrt{4 IC_q+1}-1}{2 IC_q}. \end{equation}\] The transconductance normalized to the value it takes at \(v_{id}=0\) is therefore given by \[\begin{equation} \frac{G_m}{G_{m0}} = \frac{g_m}{g_{m0}} = \frac{2}{q_s} \cdot \frac{q_{s1} \cdot q_{s2}}{q_{s1}+q_{s2}} \end{equation}\] with \(q_s\), \(q_{s1}\) and \(q_{s2}\) given by \(\eqref{eqn:qs_ICq}\), \(\eqref{eqn:qs1_iod}\) and \(\eqref{eqn:qs2_iod}\), respectively.
The normalized transconductance \(g_m\) is plotted versus the normalized differential input voltage \(v_{id}\) in Figure 5 for different values of the inversion coefficient \(IC_q\).
2 Problem 2: The inverter as a transconductance amplifier
2.1 Analysis
Assuming that both transistors are biased in weak inversion and saturation, the drain currents are then given by \[\begin{align} I_n &= I_{D0n} \cdot e^{\frac{V_{in}}{n_n U_T}},\label{eqn:In}\\ I_p &= I_{D0p} \cdot e^{\frac{V_{DD}-V_{in}}{n_p U_T}},\label{eqn:Ip} \end{align}\] where \[\begin{align} I_{D0n} &= I_{specn} \cdot e^{\frac{-V_{T0n}}{n_n U_T}},\\ I_{D0p} &= I_{specp} \cdot e^{\frac{-V_{T0p}}{n_p U_T}}, \end{align}\] with \[\begin{align} I_{specn} &= I_{specn\Box} \cdot \frac{W_n}{L_n},\\ I_{specp} &= I_{specp\Box} \cdot \frac{W_p}{L_p}. \end{align}\]
Defining \(V_b\) as the quiescent input voltage such that the output current is zero and hence \(I_p=I_n=I_b\) we can write \[\begin{equation} I_b = I_{D0n} \cdot e^{\frac{V_b}{n_n U_T}} = I_{D0p} \cdot e^{\frac{V_{DD}-V_b}{n_p U_T}}. \end{equation}\] We can then express \(I_{D0n}\) and \(I_{D0p}\) as \[\begin{align} I_{D0n} &= I_b \cdot e^{\frac{-V_b}{n_n U_T}},\label{eqn:ID0n}\\ I_{D0p} &= I_b \cdot e^{\frac{V_b-V_{DD}}{n_p U_T}}.\label{eqn:ID0p} \end{align}\] Replacing \(\eqref{eqn:ID0n}\) and \(\eqref{eqn:ID0p}\) in \(\eqref{eqn:In}\) and \(\eqref{eqn:Ip}\) results in \[\begin{align} I_n &= I_b \cdot e^{\frac{V_{in}-V_b}{n_n U_T}},\label{eqn:In2}\\ I_p &= I_b \cdot e^{-\frac{V_{in}-V_b}{n_p U_T}},\label{eqn:Ip2} \end{align}\]
The output current can then be written as \[\begin{equation} I_{out} = I_p - I_n = I_b \cdot \left[e^{-\frac{V_{in}-V_b}{n_n U_T}} - e^{\frac{V_{in}-V_b}{n_n U_T}}\right]. \end{equation}\]
Assuming that \(n_n = n_p = n\), the normalized output current can be written as \[\begin{equation} i_{out} \triangleq \frac{I_{out}}{I_b} = - 2\,\sinh(v_{in}-v_b) \end{equation}\] where \(v_{in} \triangleq V_{in}/(n U_T)\) and \(v_b \triangleq V_b/(n U_T)\).
The normalized output current is plotted in Figure 7 together with the currents of the nMOS and pMOS transistors. We see that the current is ideally not limited hence the inverter can operate as a class AB transconductance amplifier. Contrary to the differential pair where the output current is limited by the bias current \(2 I_b\), the output current of the inverter can be much larger than the bias current \(I_b\) flowing in M1 and M2 for \(V_{in}=V_b\). The current will actually be limited by the supply voltage and the supply series resistances.
2.2 Design
We want to design a CMOS inverter to be used as a trnasconductance amplifier. For this we use the schematic of Figure 8. In addition to the CMOS inverter made of M1 and M2, this circuit includes a bias circuit made of M3, M4, the current source setting the bias current \(I_b\) and the OPAMP. The bias circuit is used to prperly set the operating point of circuit in quiescent state, i.e. when \(V_{in}=0\). This is needed to control the current and therefore the inverter small-signal transconductance.The bias current imposes the current to the diode-connected transistors M3 and M4 which are made identical to M1 and M2, respectively. This generates the required bias voltage \(V_b\) to apply at the gates of M1 and M2 for their quiescent current to be equal to \(I_b\) provided the supply voltage applied to the CMOS inverter is equal to the voltage at the source of M4 (node 3). This is realized with the OPAMP which sets the supply voltage \(V_{sup}\) to be equal to the voltage at node 3 and ensures that the bias current flowing in M1 and M2 is equal to \(I_b\).
The specifications for the CMOS inverter are given in Table 1. We will design it for a generic 180nm bulk CMOS process. The physical parameters are given in Table 2, the global process parameters in Table 3 and finally the MOSFET parameters in Table 4.
| Specification | Symbol | Value | Unit |
|---|---|---|---|
| Gain-bandwidth product | \(GBW\) | 2 | \(MHz\) |
| Load capacitance | \(C_L\) | 1 | \(pF\) |
| Length of M1 | \(L_1\) | 0.5 | \(\mu m\) |
| Length of M2 | \(L_2\) | 0.5 | \(\mu m\) |
| Parameter | Value | Unit |
|---|---|---|
| \(T\) | 300 | \(K\) |
| \(U_T\) | 25.875 | \(mV\) |
| Parameter | Value | Unit |
|---|---|---|
| \(V_{DD}\) | 1.8 | \(V\) |
| \(C_{ox}\) | 8.443 | \(\frac{fF}{\mu m^2}\) |
| \(W_{min}\) | 200 | \(nm\) |
| \(L_{min}\) | 180 | \(nm\) |
| Parameter | NMOS | PMOS | Unit |
|---|---|---|---|
| sEKV parameters | |||
| \(n\) | 1.27 | 1.31 | - |
| \(I_{{spec\Box}}\) | 715 | 173 | \(nA\) |
| \(V_{{T0}}\) | 0.455 | 0.445 | \(V\) |
| \(L_{{sat}}\) | 26 | 36 | \(nm\) |
| \(\lambda\) | 15 | 20 | \(\frac{{V}}{{\mu m}}\) |
| Overlap capacitances parameters | |||
| \(C_{{GDo}}\) | 0.366 | 0.329 | \(\frac{{fF}}{{\mu m}}\) |
| \(C_{{GSo}}\) | 0.366 | 0.329 | \(\frac{{fF}}{{\mu m}}\) |
| \(C_{{GBo}}\) | 0 | 0 | \(\frac{{fF}}{{\mu m}}\) |
| Junction capacitances parameters | |||
| \(C_J\) | 1 | 1.121 | \(\frac{{fF}}{{\mu m^2}}\) |
| \(C_{{JSW}}\) | 0.2 | 0.248 | \(\frac{{fF}}{{\mu m}}\) |
| Flicker noise parameters | |||
| \(K_F\) | 8.1e-24 | 8.1e-24 | \(J\) |
| \(AF\) | 1 | 1 | - |
| \(\rho\) | 0.05794 | 0.4828 | \(\frac{{V \cdot m^2}}{{A \cdot s}}\) |
| Matching parameters | |||
| \(A_{{VT}}\) | 5 | 5 | \(mV \cdot \mu m\) |
| \(A_{{\beta}}\) | 1 | 1 | \(\% \cdot \mu m\) |
| Source and drain sheet resistance parameter | |||
| \(R_{{sh}}\) | 600 | 2386 | \(\frac{{\Omega}}{{\mu m}}\) |
| Width and length parameters | |||
| \(\Delta W\) | 39 | 54 | \(\,nm\) |
| \(\Delta L\) | -76 | -72 | \(\,nm\) |
To bias M1 and M2 in weak inversion, we choose an inversion coefficient of \(IC_1=IC_2=\) 0.1. The gain-bandwidth product \(GBW\) is set by the inverter transconductance \(G_{meq}\) and the load capacitance \(C_L\) according to \[\begin{equation} GBW = \frac{G_{meq}}{2\pi\,C_L}, \end{equation}\] where the inverter transcondcutance \(G_{meq}\) is simply the sum of the nMOS and pMOS transcondcutances \[\begin{equation} G_{meq} = G_{m1} + G_{m2} \end{equation}\] In weak inversion, the two transconductances are given by \[\begin{align} G_{m1} &= \frac{I_b}{n_1\,U_T},\\ G_{m2} &= \frac{I_b}{n_2\,U_T}. \end{align}\] and hence \[\begin{equation} G_{meq} = \frac{I_b}{U_T} \,\left(\frac{1}{n_1}+\frac{1}{n_2}\right). \end{equation}\] If the slope factors can be considered as equal \(n_1=n_2=n\), then \(G_{m1}=G_{m2}\). Acounting for the fact that M1 and M2 are note biased in deep weak inversion we have \[\begin{equation} G_{meq} =\frac{I_b}{U_T}\,\left(\frac{gmsid(IC_1)}{n_1}+\frac{gmsid(IC_2)}{n_2}\right), \end{equation}\] where \[\begin{equation} gmsid = \frac{G_m\,n U_T}{I_D} \end{equation}\] is the normalized \(G_m/I_D\) function. In our case \(IC_1=IC_2=IC\) and hence \[\begin{equation} G_{meq} =\frac{I_b\,gmsid(IC)}{U_T}\,\left(\frac{1}{n_1}+\frac{1}{n_2}\right), \end{equation}\] We can then deduce the bias current as \[\begin{equation} I_b = \frac{G_{meq}\,U_T}{gmsid(IC)\,(1/n_1+1/n_2)} \end{equation}\]
The bias current is set to \(I_b =\) 229 \(nA\). We can now get the specific currents as \(I_{spec1} = I_b/IC_1 =\) 2.287 \(\mu A\) and \(I_{spec2} = I_b/IC_2 =\) 2.287 \(\mu A\) from which we deduce the aspect ratioes \(W_1/L_1 =\) 3.198 and \(W_2/L_2 =\) 13.207. Knowing the length we get the width \(W_1 =\) 1.60 \(\mu m\) and \(W_2 =\) 6.60 \(\mu m\).
2.3 Simulation
2.3.1 DC transfer characteristic
To simulate the DC transfer characteristic \(I_{out}\) versu \(V_{in}\), we will use the schematic shown in Figure 9. We first check the operating point looking at the quiescent voltages which are presented in Table 5.
| Node | Voltage |
|---|---|
| vdd | 1.8 |
| vsup | 0.826433 |
| vb | 0.418316 |
| out | 0.418316 |
| 1 | 0.418316 |
| 2 | 0.418316 |
| 3 | 0.826434 |
| d1 | 0.418316 |
| d2 | 0.418316 |
The large-signal transfer characteristic is shown in Figure 10.
Figure 10 clearly illustrates the class AB operation of the CMOS inverter and its ability to deliver an output current that is much larger than the bias current. We can zoom into the region close to the operating as shown in Figure 11.
2.3.2 Open-loop transfer function
We can also simulate the open-loop transfer function which is plotted in Figure 12 and compared to the theoretical estimation. We see that the gain-bandwidth product perfectly matches the simulation and is right on target. The simulated DC gain is slightly larger tha the theoretical estimation. This simply comes from the simple output conductance model which is not very accurate.
3 Problem 3: Effect of velocity saturation on the gate transconductance
3.1 Strong inversion
For the strong inversion case we assume a bias current \(I_b=\) 20 \(\mu A\), an inversion coefficient \(IC =\) 30 and load capacitance \(C_L =\) 1 \(pF\).
3.1.1 Long-channel case
For the long-channel case the normalized source transconductance is given by \[\begin{equation} g_{ms} = \frac{\sqrt{4 IC+1}-1}{2}, \end{equation}\] which for the given inversion coefficient \(IC =\) 30 gives \(g_{ms} \triangleq G_m/G_{spec} =\) 5. Knowing the bias current \(I_b=\) 20 \(\mu A\) and the inversion coefficient \(IC =\) 30, we can deduce the specific current as \(I_{spec} = I_b/IC =\) 667 \(nA\). The gate transconductance is then given by \[\begin{equation} G_m = G_{spec} \cdot \frac{g_{ms}}{n} = \frac{I_{spec}}{n\cdot U_T} \cdot g_{ms}, \end{equation}\] which is equal to \(G_m =\) 128.2 \(\mu A/V\). The corresponding bandwidth is then given by \(BW = G_m/(2 \pi\,C_L) =\) 20.4 \(MHz\).
3.1.2 Short-channel case
For the short-channel case, the normalized source transconductance now also depends on the velocity saturation parameter \(\lambda_c\) according to \[\begin{equation} g_{ms} = \frac{\sqrt{4 IC+1+(\lambda_c\,IC)^2}-1}{2+\lambda_c^2\,IC}. \end{equation}\] For \(\lambda_c =\) 0.333 and \(IC =\) 30, we get \(g_{ms} =\) 2.600. Keeping the same current \(I_b=\) 20 \(\mu A\) and inversion coefficient \(IC =\) 30 and assuming that \(I_{spec}\) remains the same, we get \(G_m = I_{spec}/(n U_T) \cdot g_{ms} =\) 66.664 \(\mu A/V\), which is 1.923 times smaller than what we get for the long-channel case. The corresponding bandwidth is now reduced accordingly to \(BW = G_m/(2 \pi\,C_L) =\) 10.6 \(MHz\).
3.2 Weak inversion
In the case of weak inversion we assume an inversion coefficient \(IC =\) 0.1, a bias current \(I_b=\) 100 \(nA\) and a load capacitance \(C_L =\) 0.1 \(pF\).
3.2.1 Long-channel case
For the long-channel case the normalized source transconductance is given by \(g_{ms} \triangleq G_m/G_{spec} =\) 0.092. Knowing the bias current \(I_b=\) 100 \(\mu A\) and the inversion coefficient \(IC =\) 0.1, we can deduce the specific current as \(I_{spec} = I_b/IC =\) 1 \(\mu A\). The gate transconductance is then given by \(G_m =\) 3.523 \(\mu A/V\) and the corresponding bandwidth is equal to \(BW = G_m/(2 \pi\,C_L) =\) 5.6 \(MHz\).
3.2.2 Short-channel case
For the short-channel case, the normalized source transconductance is given by \(g_{ms} =\) 0.091 which is almost equal to what we got for the long-channel case in weak inversion. This is expected since velocity saturation has no effect in weak inversion.
Keeping the same current \(I_b=\) 100 \(nA\) and inversion coefficient \(IC =\) 0.1 and assuming that \(I_{spec}\) remains the same, we get \(G_m = I_{spec}/(n U_T) \cdot g_{ms} =\) 3.513 \(\mu A/V\), which is about equal to what we got for the long-channel case. The corresponding bandwidth is also unchanged \(BW = G_m/(2 \pi\,C_L) =\) 5.6 \(MHz\).
This example shows that velocity saturation reduces the transconductance that we get for a given current and inversion coefficient. For best current efficiency, we should move to moderate or even weak inversion to avoid the effect of velocity saturation. Now, moving the operating point to weak inversion results in a much lower transconductance and therefore bandwidth for a given capacitance. It also leads to large transistors and large parasisics.