Common Source Amplifier Design
Christian Enz
Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland
This notebook presents the design of a simple common-source transistor for various specifications. The objective is to make the student more familiar to the concept of inversion coefficient $IC$ and the $G_m/I_D$ design methodology.
To run the simulation you first need to install Smash on your computer. Please follow the instructions given in the Moodle site.
We will use the parameters given below that correspond to a generic 180nm bulk CMOS process.
Main physical parameters: ═════════════════════════
Main process parameters for TSMC 0.18um: ════════════════════════════════════════
nNMOS parameters: ═════════════════ Long-channel sEKV parameters: ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Overlap capacitances: ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Junction capacitances: ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
1/f noise parameters: ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Matching parameters: ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Source and drain sheet resistance: ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Channel width and length corrections ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Schematic of the common-source (CS) loaded by capacitor $C_L$.
In this first example we will design the CS shown in the above figure for the specifications at room temperature given below by imposing the inversions coefficient and the load capacitance:
Small-signal schematic of the common-source (CS).
The small-signal schematic of the CS amplifier is shown in the above figure. The transfer function is given by
\begin{equation*} H(s) \triangleq \frac{\Delta V_{out}}{\Delta V_{in}} = \frac{A_{dc}}{1+\frac{s}{\omega_c}}, \end{equation*}where $A_{dc} = -G_m/G_{ds}$ is the dc gain and $\omega_c = G_{ds}/C_L$ the cut-off frequency.
The magnitude of the frequency response is then given by
\begin{equation*} |H(\omega)| = \frac{|A_{dc}|}{\sqrt{1+\left(\frac{\omega}{\omega_c}\right)^2}} \cong \frac{\omega_u}{\omega} \end{equation*}for $\omega_c \ll \omega$ where
\begin{equation*} \omega_u = |A_{dc}| \cdot \omega_c = \frac{G_m}{C_L} \end{equation*}is the unity-gain frequency or gain-bandwidth product.
The specifications for Problem 1 are given below.
For the long-channel case, we take:
We can calculate the required transconductance $G_m$ from the GBW product and the constant load capacitance as
Assuming a long-channel transistor we can neglect the effect of velocity saturation and calculate the current efficiency for the chosen inversion coefficient as
By definition of the current efficiency we can get the corresponding bias current
From the bias current and the inversion coefficient we get the specific current as
The W/L is the simply given by
From which we get the effective and drawn width
We can check what is the resulting dc gain by estimating the output conductance
We also calculate the area and perimeter of the drain to estimate the junction capacitance and overlap capacitance in order to correct $C_L$ to get the correct $GBW$.
Schematic of the common-source (CS) gain stage used for simulation.
We can now check whether we get the correct GBW and DC gain using Smash simulations with the schematic shown in the above figure, where transistor $M_2$ is used to correctly bias the gate of the CS transistor $M_1$ for the desired bias current $I_b$. Notice that transistor $M_2$ has been made noiseless so that we only get the noise of $M_1$.
The simulations will be performed with the following parameters.
.param VDD=1.8 Ib=33.44u .param CL=949f .param W=43.18u L=1u AD=1.73e-11 PD=8.72e-05 .param fdec=101 fmin=1k fmax=1G
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 6.688e-05 on VDD Iteration 2, residual 1.439e-03 on M2::DI Iteration 3, residual 8.343e-04 on M1::DI Iteration 4, residual 4.424e-04 on M1::DI Iteration 5, residual 2.113e-04 on M1::DI Iteration 6, residual 8.880e-05 on M1::DI Iteration 7, residual 3.090e-05 on M2::DI Iteration 8, residual 7.432e-06 on M2::DI Iteration 9, residual 7.420e-07 on M2::DI Iteration 10, residual 9.422e-09 on M2::DI Iteration 11, residual 1.576e-12 on M1::DI Operating point analysis completed (converged) Small Signal Small signal analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s 250ms Elapsed Time: 6s 903ms 945us
Adc = 51.632 dB GBW = 9.758e+01 MHz Dominant pole fp1 = 255.230 kHz
The simulated GBW and DC gain almost match the target specs.
For the short-channel case we will use the shortest channel length for this technology, namely:
The velocity parameter for the chosen length is then given by
The procedure is then the same: we first get the bias current from the current efficiency but including the effect of velocity saturation
We see that the current efficiency $G_m n U_T/I_D$ is slightly smaller than for the long-channel case due to velocity saturation.
The bias current is then given by
Despite we use a shorter channel-length, the required bias current is about the same than the one from the long-channel case. This is due to velocity saturation which reduces the current efficiency even at $IC=1$.
From the bias current and the inversion coefficient we get the specific current as
The W/L is the simply given by
From which we get the effective and drawn width
We can check what is the resulting dc gain by estimating the output conductance
We also calculate the area and perimeter of the drain to calculate the junction capacitance and overlap capacitance in order to correct $C_L$ to get the correct $GBW$.
We can check whether we get the correct GBW and dc gain using Smash simulations with the following values of the parameters:
.param VDD=1.8 Ib=35.18u .param CL=994f .param W=5.08u L=0.18u AD=2.03e-12 PD=1.10e-05 .param fdec=101 fmin=1k fmax=1G
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 7.036e-05 on VDD Iteration 2, residual 9.759e-04 on M2::DI Iteration 3, residual 5.837e-04 on M2::DI Iteration 4, residual 3.139e-04 on M2::DI Iteration 5, residual 1.484e-04 on M2::DI Iteration 6, residual 5.880e-05 on M2::DI Iteration 7, residual 1.751e-05 on M2::DI Iteration 8, residual 2.877e-06 on M2::DI Iteration 9, residual 1.141e-07 on M2::DI Iteration 10, residual 1.983e-10 on M2::DI Operating point analysis completed (converged) Small Signal Small signal analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s 125ms Elapsed Time: 6s 193ms 675us
Adc = 32.199 dB GBW = 9.521e+01 MHz Dominant pole fp1 = 2337.800 kHz
The DC gain is above specs, however the GBW is slightly below specs. This would require some additional fine tuning.
We now impose the power consumption, the inversion coefficient and the load capacitance:
For the long-channel case, we have:
The maximum available current is directly given by
Since the inversion coefficient is chosen we get the specific current as
The normalized transconductance is the given by the chosen inversion coefficient
From which we derive the transconductance and the gain-bandwidth product for the load capacitance
The W/L is then obtained from
and finally the effective width and drawn width are given by
We can calculate the dc gain by first estimating the output conductance
We also calculate the area and perimeter of the drain to calculate the junction capacitance and overlap capacitance in order to correct $C_L$ to get the correct $GBW$.
We can check whether we get the correct GBW and dc gain using Smash simulations with the following values of the parameters:
.param VDD=1.8 Ib=55.56u .param CL=916f .param W=71.76u L=1.00u AD=2.87e-11 PD=1.44e-04 .param fdec=101 fmin=1k fmax=1G
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 1.111e-04 on VDD Iteration 2, residual 2.390e-03 on M2::DI Iteration 3, residual 1.386e-03 on M1::DI Iteration 4, residual 7.349e-04 on M1::DI Iteration 5, residual 3.511e-04 on M1::DI Iteration 6, residual 1.475e-04 on M1::DI Iteration 7, residual 5.133e-05 on M2::DI Iteration 8, residual 1.235e-05 on M2::DI Iteration 9, residual 1.232e-06 on M2::DI Iteration 10, residual 1.564e-08 on M2::DI Iteration 11, residual 2.615e-12 on M1::DI Operating point analysis completed (converged) Small Signal Small signal analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s 156ms 250us Elapsed Time: 6s 281ms 289us
Adc = 51.632 dB GBW = 1.630e+02 MHz Dominant pole fp1 = 424.970 kHz
The simulated GBW and DC gain are close to the theoretical results.
For the short-channel case we will use the shortest channel length for this technology, namely:
The procedure is basically the same except that we now need to account for velocity saturation.
We see that the gain-bandwidth is now slightly smaller than what we obtained for the long-channel case. This illustrates the impact of velocity saturation which reduces the transconductance for a given current particularly in strong inversion. It will also have an impact on the dc gain since not only $G_m$ is smaller but $G_{ds}$ gets large because of the minimum channel length.
We also calculate the area and perimeter of the drain to calculate the junction capacitance and overlap capacitance in order to correct $C_L$ to get the correct $GBW$.
We can check whether we get the correct GBW and dc gain using LTspice simulations with the schematic given in Fig. \ref{fig:Problem1_long_schematic}.
The simulations will be performed for the following values of the parameters:
.param VDD=1.8 Ib=55.56u .param CL=990f .param W=8.04u L=0.18u AD=3.22e-12 PD=1.69e-05 .param fdec=101 fmin=1k fmax=1G
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 1.111e-04 on VDD Iteration 2, residual 1.540e-03 on M2::DI Iteration 3, residual 9.212e-04 on M2::DI Iteration 4, residual 4.954e-04 on M2::DI Iteration 5, residual 2.342e-04 on M2::DI Iteration 6, residual 9.279e-05 on M2::DI Iteration 7, residual 2.763e-05 on M2::DI Iteration 8, residual 4.536e-06 on M2::DI Iteration 9, residual 1.796e-07 on M2::DI Iteration 10, residual 3.112e-10 on M2::DI Operating point analysis completed (converged) Small Signal Small signal analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s 187ms 500us Elapsed Time: 6s 134ms 383us
Adc = 32.198 dB GBW = 1.504e+02 MHz Dominant pole fp1 = 3694.300 kHz
The simulated GBW and DC gain are close to the target specs.
We now do not impose the inversion coefficient but the gain bandwidth product and the current budget. We keep the same load capacitance and consider a long channel.
We first get the transconductance required to achieve the target gain-bandwidth product
Knowing the bias current and the transconductance we can calculate the current efficiency as
from which we can derive the corresponding inversion coefficient by
We see that we are in the moderate inversion region. The specific current is then given by
The W/L ratio is then obtained as
and finally the effective and drawn width
The dc gain is directly estimated from the transconductance and the output conductance
We also calculate the area and perimeter of the drain to calculate the junction capacitance and overlap capacitance in order to correct $C_L$ to get the correct $GBW$.
We observe that the parasitic capacitance at the drain are negligible compared to the load capacitance.
We can check whether we get the correct GBW and dc gain using the following values of the parameters:
.param VDD=1.8 Ib=400n .param CL=1000f .param W=0.25u L=1u AD=1.00e-13 PD=1.30e-06 .param fdec=101 fmin=10 fmax=10MEG
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 8.000e-07 on VDD Iteration 2, residual 9.619e-06 on M2::DI Iteration 3, residual 5.566e-06 on M1::DI Iteration 4, residual 2.932e-06 on M1::DI Iteration 5, residual 1.372e-06 on M1::DI Iteration 6, residual 5.442e-07 on M1::DI Iteration 7, residual 1.611e-07 on M2::DI Iteration 8, residual 2.497e-08 on M2::DI Iteration 9, residual 8.369e-10 on M2::DI Iteration 10, residual 1.011e-12 on M2::DI Operating point analysis completed (converged) Small Signal Small signal analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s Elapsed Time: 6s 46ms 767us
Adc = 50.874 dB GBW = 9.623e-01 MHz Dominant pole fp1 = 2.752 kHz
The simulated GBW and DC gain are almost on specs.
In this example, we impose the input-referred noise by setting the white noise and corner frequency.
We need the flicker noise parameter $K_f$ and the oxide capacitance per unit area $C_{ox}$
Before deriving the transconductance is derived from the thermal noise specification we need to know the thermal noise excess factor for the given $IC$ (we assume long-channel case)
The transconductance is then given by
Once we have the transconductance, the procedure is similar to the previous one. Having imposed the inversion coefficient we can deduce the current efficiency factor as
By definition of the current efficiency we can get the corresponding bias current
From the bias current and the inversion coefficient we get the specific current as
The W/L ratio is then obtained as
The corner frequency will actually set the flicker noise which is inversely proportional to the gate are. We can therefore calculate the gate area from the flicker noise remembering that the corner frequency is the frequency at which the flicker noise becomes equal to the white noise
Finally we can also calculate the gain-bandwidth product
The dc gain is directly estimated from the transconductance and the output conductance
We also calculate the area and perimeter of the drain to calculate the junction capacitance and overlap capacitance in order to correct $C_L$ to get the correct $GBW$.
We can check whether we get the correct GBW and dc gain using the following values of the parameters:
.param VDD=1.8 Ib=0.70u .param CL=996f .param W=3.20u L=3.37u AD=1.28e-12 PD=7.20e-06 .param fdec=101 fmin=10 fmax=10MEG
We first can check the small-signal gain.
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 1.400e-06 on VDD Iteration 2, residual 3.480e-05 on M2::DI Iteration 3, residual 2.031e-05 on M1::DI Iteration 4, residual 1.091e-05 on M1::DI Iteration 5, residual 5.323e-06 on M1::DI Iteration 6, residual 2.308e-06 on M1::DI Iteration 7, residual 8.482e-07 on M2::DI Iteration 8, residual 2.299e-07 on M2::DI Iteration 9, residual 3.074e-08 on M2::DI Iteration 10, residual 7.572e-10 on M2::DI Iteration 11, residual 4.899e-13 on M2::DI Operating point analysis completed (converged) Small Signal Small signal analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s 31ms 250us Elapsed Time: 5s 999ms 686us
Adc = 62.501 dB GBW = 2.043e+00 MHz Dominant pole fp1 = 1.532 kHz
We can now check the input-referred noise.
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 1.400e-06 on VDD Iteration 2, residual 3.480e-05 on M2::DI Iteration 3, residual 2.031e-05 on M1::DI Iteration 4, residual 1.091e-05 on M1::DI Iteration 5, residual 5.323e-06 on M1::DI Iteration 6, residual 2.308e-06 on M1::DI Iteration 7, residual 8.482e-07 on M2::DI Iteration 8, residual 2.299e-07 on M2::DI Iteration 9, residual 3.074e-08 on M2::DI Iteration 10, residual 7.572e-10 on M2::DI Iteration 11, residual 4.899e-13 on M2::DI Operating point analysis completed (converged) Noise Noise analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s Elapsed Time: 6s 31ms 638us
The simulated input-referred white noise and corner frequency are perfectly on target.
Schematic of the common-source (CS) illustrating the self-loading effect.
In this problem we want to find the minimum current required to achieve a given gain-bandwidth product accounting for the effect of self-loading as illustrated in the above figure.
We will use the following specifications:
For accounting for the self-loading effect we need the capacitance per width $C_{DW}$
We first calculate the various normalization parameters
The dc gain is directly estimated from the transconductance and the output conductance
We also calculate the area and perimeter of the drain to calculate the junction capacitance and overlap capacitance in order to correct $C_L$ to get the correct $GBW$.
We can check whether we get the correct GBW and DC gain using Smash simulations. The simulations will be performed for the following values of the parameters:
.param VDD=1.8 Ib=122n .param CL=18.1f .param W=1.46u L=1u AD=5.84e-13 PD=3.72e-06 .param fdec=101 fmin=1k fmax=100MEG
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 2.440e-07 on VDD Iteration 2, residual 4.992e-05 on M2::DI Iteration 3, residual 2.901e-05 on M2::DI Iteration 4, residual 1.549e-05 on M2::DI Iteration 5, residual 7.565e-06 on M2::DI Iteration 6, residual 3.388e-06 on M2::DI Iteration 7, residual 1.407e-06 on M2::DI Iteration 8, residual 5.470e-07 on M2::DI Iteration 9, residual 1.948e-07 on M2::DI Iteration 10, residual 5.688e-08 on M2::DI Iteration 11, residual 9.858e-09 on M2::DI Iteration 12, residual 4.545e-10 on M2::DI Iteration 13, residual 1.081e-12 on M2::DI Operating point analysis completed (converged) Small Signal Small signal analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s 203ms 125us Elapsed Time: 6s 47ms 610us
Adc = 52.904 dB GBW = 2.667e+01 MHz Dominant pole fp1 = 60.295 kHz
The simulated GBW is slightly larger than specs and the DC gain is slightly lower than the theoretical result (it is not a spec in this problem).
In this problem we want to find the minimum current required to achieve a given gain-bandwidth product and a given dc gain accounting for the effect of self-loading. We will use the following specs:
We first calculate the various normalization parameters
We also calculate the area and perimeter of the drain to calculate the junction capacitance and overlap capacitance in order to correct $C_L$ to get the correct $GBW$.
We can check whether we get the correct GBW and DC gain using Smash simulations.
.param VDD=1.8 Ib=111n .param CL=19.1f .param W=0.62u L=0.25u AD=2.48e-13 PD=2.04e-06 .param fdec=101 fmin=1k fmax=100MEG
Starting Smash simulation... ---------------------------------------------------------------------- - - SMASH (TM) release 7.6.0 (64-bit) of Jun 30 2020 - Copyright (c) Dolphin Design, 1992-2020. All Rights Reserved. - ---------------------------------------------------------------------- Output directory L:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash Parsing circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Loading circuit l:\My Drive\Lectures\Master\Fundamentals of Analog VLSI Design\2024\Exercises\2024.10.16\Jupyter Notebook\Simulations\Smash\csamp.pat Processing top-level Elaborating circuit... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Elaborating circuit (logic)... Elaborating circuit (creating devices)... Elaborating circuit (elaborating devices)... Initializing... Searching for HZ nets: 0% Linking analog resolution matrix... Load completed. Operating-Point analysis (trying logarithmic damping heuristics)... Iteration 1, residual 2.220e-07 on VDD Iteration 2, residual 8.405e-05 on M2::DI Iteration 3, residual 4.947e-05 on M2::DI Iteration 4, residual 2.644e-05 on M2::DI Iteration 5, residual 1.272e-05 on M2::DI Iteration 6, residual 5.544e-06 on M2::DI Iteration 7, residual 2.259e-06 on M2::DI Iteration 8, residual 8.869e-07 on M2::DI Iteration 9, residual 3.343e-07 on M2::DI Iteration 10, residual 1.136e-07 on M2::DI Iteration 11, residual 2.910e-08 on M2::DI Iteration 12, residual 3.536e-09 on M2::DI Iteration 13, residual 7.007e-11 on M2::DI Iteration 14, residual 2.886e-14 on M1::DI Operating point analysis completed (converged) Small Signal Small signal analysis completed Launch Measurements: 6 End Measurements CPU Time: 5s 109ms 375us Elapsed Time: 6s 206ms 579us
Adc = 38.339 dB GBW = 2.559e+01 MHz Dominant pole fp1 = 309.680 kHz
The simulated GBW is slightly above spec, whereas the simulated DC gain is slightly lower than spec.
This exercise has illustrated how to design (i.e. choose the bias current and the device size) a simple common-source amplifier using the inversion coefficient and the related functions for various specifications. It has been shown that a good fit to the specifications can be achieved in various modes of operation. It also has shown the limitation of the output conductance model which can only be used in a restricted region of operation. However it gives a first order result which can be further optimized by simulations.