Small-signal equivalent circuit.
The above figure represents the small-signal schematic of the differential pair, where $Y_s$ corresponds to the admittance to ground at the common source node made of the output conductance of the bottom current source and the total capacitance between the common source node and ground.
If the transistors and resistances are perfectly matched, in small-signal operation (ie. $G_{m1}=G_{m2}=G_m$ and $R_1=R_2=R$), an increase of the gate voltage of $M_1$ by $\Delta V_{id}/2$ combined with a decrease of the gate voltage of $M_2$ by the same amount keeps the common source node unchanged. This node can therefore be considered as a virtual ac ground. The circuit then reduces to a common-source stage loaded ba a resistance $R$ which has a voltage gain $-G_m\,R$. The differential stage has therefore the same ideal voltage gain $A_{vd}=-G_m\,R$.
Of course we can find this results by solving the KCL of the above equivalent small-signal circuit. Writing the KCL for the three nodes leads to
\begin{align*}
G_{m1}\,\Delta V_{G1} + \Delta V_{o1}/R_1 &= 0,\\
G_{m2}\,\Delta V_{G2} + \Delta V_{o2}/R_2 &= 0,\\
G_{m1}\,\Delta V_{G1} + G_{m2}\,\Delta V_{G2} &= Y_s\,\Delta V_S.
\end{align*}
Additionally, the incremental gate voltages are related to the input voltages according to
\begin{align*}
\Delta V_{G1} &= \Delta V_{i1} - \Delta V_S,\\
\Delta V_{G2} &= \Delta V_{i2} - \Delta V_S.
\end{align*}
Solving the above equations together, we obtain the incremental output voltages as
\begin{align*}
\Delta V_{o1} &= -G_{m1}\,R_1 \cdot \frac{(G_{m2}+Y_s)\,\Delta V_{i1}-G_{m2}\Delta V_{i2}}{G_{m1}+G_{m2}+Y_s},\\
\Delta V_{o2} &= -G_{m2}\,R_2 \cdot \frac{-G_{m1}\Delta V_{i1}+(G_{m1}+Y_s)\Delta V_{i2}}{G_{m1}+G_{m2}+Y_s}.
\end{align*}
We now express the output voltages in terms of the differential and common mode voltages $\Delta V_{id}$ and $\Delta V_{ic}$ defined as
\begin{align*}
\Delta V_{id} &\triangleq \Delta V_{i1} - \Delta V_{i2},\\
\Delta V_{ic} &\triangleq \frac{\Delta V_{i1} + \Delta V_{i2}}{2},
\end{align*}
such that
\begin{align*}
\Delta V_{i1} &= \Delta V_{ic} + \frac{\Delta V_{id}}{2},\\
\Delta V_{i2} &= \Delta V_{ic} - \frac{\Delta V_{id}}{2}.
\end{align*}
The differential and common modes of operation are then defined for $\Delta V_{ic} = 0$ and for $\Delta V_{id} = 0$, respectively.
The differential voltage gain, is then defined as
\begin{equation*}
A_{vd} \triangleq \frac{\Delta V_{od}}{\Delta V_{id}} = \frac{\Delta V_{o1} - \Delta V_{o2}}{\Delta V_{id}}.
\end{equation*}
The differential voltage gain is obtained as
\begin{equation*}
A_{vd} = -\frac{G_{m1}\,G_{m2}\,(R_1+R_2)+(G_{m1}R_1+G_{m2}R_2)Y_s/2}{G_{m1}+G_{m2}+Y_s}.
\end{equation*}
Assuming that the transistors and resistances are perfectly matched $G_{m1}=G_{m2}=G_m$ and $R_1=R_2=R$, the expression for the differential voltage gain simplifies to the expected result
\begin{equation*}
A_{vd} = -G_m\,R.
\end{equation*}
One of the main feature of the differential pair is to reject the input common-mode voltage. In the case the transistors and resistances are perfectly matched, the common-mode to differential output voltage gain is ideally equal to zero because $\Delta V_{o1}=\Delta V_{o2}$. However, if there is a mismatch between the transistors or the resistances, $V_{o1} \neq V_{o2}$ and therefore a differential output voltage is generated. The common-mode to differential voltage gain is given by
\begin{equation*}
A_{vc} = Y_s \cdot \frac{G_{m2}\,R_2-G_{m1}\,R_1}{G_{m1}+G_{m2}+Y_s}
\end{equation*}
From the above equation, we see that for a perfect matching $A_{vc}=0$ since $G_{m1}\,R_1 = G_{m2}\,R_2$. At low frequency, $Y_s$ is equal to the output conductance $G_{ds}$ of the bottom current source. The common-mode to differential voltage gain is proportional to $G_{ds}$. We can account for the mismatch by replacing
\begin{align*}
G_{m1} &= G_m + \frac{\Delta G_m}{2},\\
G_{m2} &= G_m - \frac{\Delta G_m}{2},\\
R_1 &= R + \frac{\Delta R}{2},\\
R_2 &= R - \frac{\Delta R}{2},
\end{align*}
resulting in
\begin{equation*}
A_{vc} = -G_{ds} \cdot \frac{G_m\,R}{G_{ds}+2G_m} \cdot \left(\frac{\Delta G_m}{G_m} + \frac{\Delta R}{R}\right)
\cong - \frac{G_{ds}\,R}{2} \left(\frac{\Delta G_m}{G_m} + \frac{\Delta R}{R}\right),
\end{equation*}
since $G_m \gg G_{ds}$.
The ability of the differential pair to reject the differential voltage is measured by the common-mode rejection ratio or CMRR defined as
\begin{equation*}
CMRR \triangleq \frac{|A_{vd}|}{|A_{vc}|} \cong \frac{2 G_m/G_{ds}}{\frac{\Delta G_m}{G_m} + \frac{\Delta R}{R}}.
\end{equation*}
